Merge pull request #2693 from ReinUsesLisp/hsetp2
shader/half_set_predicate: Implement missing HSETP2 variants
This commit is contained in:
commit
0a67416971
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@ -931,8 +931,6 @@ union Instruction {
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} csetp;
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} csetp;
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union {
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union {
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BitField<35, 4, PredCondition> cond;
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BitField<49, 1, u64> h_and;
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BitField<6, 1, u64> ftz;
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BitField<6, 1, u64> ftz;
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BitField<45, 2, PredOperation> op;
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BitField<45, 2, PredOperation> op;
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BitField<3, 3, u64> pred3;
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BitField<3, 3, u64> pred3;
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@ -940,9 +938,21 @@ union Instruction {
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BitField<43, 1, u64> negate_a;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_a;
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BitField<44, 1, u64> abs_a;
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BitField<47, 2, HalfType> type_a;
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BitField<47, 2, HalfType> type_a;
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BitField<31, 1, u64> negate_b;
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union {
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BitField<30, 1, u64> abs_b;
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BitField<35, 4, PredCondition> cond;
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BitField<28, 2, HalfType> type_b;
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BitField<49, 1, u64> h_and;
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BitField<31, 1, u64> negate_b;
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BitField<30, 1, u64> abs_b;
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BitField<28, 2, HalfType> type_b;
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} reg;
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union {
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BitField<56, 1, u64> negate_b;
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BitField<54, 1, u64> abs_b;
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} cbuf;
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union {
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BitField<49, 4, PredCondition> cond;
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BitField<53, 1, u64> h_and;
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} cbuf_and_imm;
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BitField<42, 1, u64> neg_pred;
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BitField<42, 1, u64> neg_pred;
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BitField<39, 3, u64> pred39;
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BitField<39, 3, u64> pred39;
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} hsetp2;
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} hsetp2;
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@ -1548,7 +1558,9 @@ public:
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HFMA2_RC,
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HFMA2_RC,
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HFMA2_RR,
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HFMA2_RR,
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HFMA2_IMM_R,
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HFMA2_IMM_R,
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HSETP2_C,
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HSETP2_R,
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HSETP2_R,
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HSETP2_IMM,
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HSET2_R,
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HSET2_R,
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POPC_C,
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POPC_C,
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POPC_R,
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POPC_R,
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@ -1831,7 +1843,9 @@ private:
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INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"),
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INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"),
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INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"),
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INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"),
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INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"),
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INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP_R"),
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INST("0111111-1-------", Id::HSETP2_C, Type::HalfSetPredicate, "HSETP2_C"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
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INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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@ -254,10 +254,6 @@ public:
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}
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}
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private:
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private:
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using OperationDecompilerFn = std::string (GLSLDecompiler::*)(Operation);
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using OperationDecompilersArray =
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std::array<OperationDecompilerFn, static_cast<std::size_t>(OperationCode::Amount)>;
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void DeclareVertex() {
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void DeclareVertex() {
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if (stage != ShaderStage::Vertex)
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if (stage != ShaderStage::Vertex)
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return;
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return;
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@ -1400,14 +1396,10 @@ private:
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return fmt::format("{}[{}]", pair, VisitOperand(operation, 1, Type::Uint));
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return fmt::format("{}[{}]", pair, VisitOperand(operation, 1, Type::Uint));
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}
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}
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std::string LogicalAll2(Operation operation) {
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std::string LogicalAnd2(Operation operation) {
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return GenerateUnary(operation, "all", Type::Bool, Type::Bool2);
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return GenerateUnary(operation, "all", Type::Bool, Type::Bool2);
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}
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}
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std::string LogicalAny2(Operation operation) {
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return GenerateUnary(operation, "any", Type::Bool, Type::Bool2);
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}
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template <bool with_nan>
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template <bool with_nan>
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std::string GenerateHalfComparison(Operation operation, const std::string& compare_op) {
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std::string GenerateHalfComparison(Operation operation, const std::string& compare_op) {
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const std::string comparison{GenerateBinaryCall(operation, compare_op, Type::Bool2,
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const std::string comparison{GenerateBinaryCall(operation, compare_op, Type::Bool2,
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@ -1714,7 +1706,7 @@ private:
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return "utof(gl_WorkGroupID"s + GetSwizzle(element) + ')';
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return "utof(gl_WorkGroupID"s + GetSwizzle(element) + ')';
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}
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}
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static constexpr OperationDecompilersArray operation_decompilers = {
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static constexpr std::array operation_decompilers = {
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&GLSLDecompiler::Assign,
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&GLSLDecompiler::Assign,
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&GLSLDecompiler::Select,
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&GLSLDecompiler::Select,
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@ -1798,8 +1790,7 @@ private:
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&GLSLDecompiler::LogicalXor,
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&GLSLDecompiler::LogicalXor,
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&GLSLDecompiler::LogicalNegate,
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&GLSLDecompiler::LogicalNegate,
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&GLSLDecompiler::LogicalPick2,
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&GLSLDecompiler::LogicalPick2,
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&GLSLDecompiler::LogicalAll2,
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&GLSLDecompiler::LogicalAnd2,
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&GLSLDecompiler::LogicalAny2,
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&GLSLDecompiler::LogicalLessThan<Type::Float>,
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&GLSLDecompiler::LogicalLessThan<Type::Float>,
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&GLSLDecompiler::LogicalEqual<Type::Float>,
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&GLSLDecompiler::LogicalEqual<Type::Float>,
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@ -1863,6 +1854,7 @@ private:
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&GLSLDecompiler::WorkGroupId<1>,
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&GLSLDecompiler::WorkGroupId<1>,
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&GLSLDecompiler::WorkGroupId<2>,
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&GLSLDecompiler::WorkGroupId<2>,
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};
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};
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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std::string GetRegister(u32 index) const {
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std::string GetRegister(u32 index) const {
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return GetDeclarationWithSuffix(index, "gpr");
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return GetDeclarationWithSuffix(index, "gpr");
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@ -205,10 +205,6 @@ public:
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}
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}
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private:
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private:
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using OperationDecompilerFn = Id (SPIRVDecompiler::*)(Operation);
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using OperationDecompilersArray =
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std::array<OperationDecompilerFn, static_cast<std::size_t>(OperationCode::Amount)>;
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static constexpr auto INTERNAL_FLAGS_COUNT = static_cast<std::size_t>(InternalFlag::Amount);
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static constexpr auto INTERNAL_FLAGS_COUNT = static_cast<std::size_t>(InternalFlag::Amount);
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void AllocateBindings() {
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void AllocateBindings() {
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@ -804,12 +800,7 @@ private:
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return {};
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return {};
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}
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}
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Id LogicalAll2(Operation operation) {
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Id LogicalAnd2(Operation operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id LogicalAny2(Operation operation) {
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UNIMPLEMENTED();
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UNIMPLEMENTED();
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return {};
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return {};
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}
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}
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@ -1206,7 +1197,7 @@ private:
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return {};
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return {};
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}
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}
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static constexpr OperationDecompilersArray operation_decompilers = {
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static constexpr std::array operation_decompilers = {
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&SPIRVDecompiler::Assign,
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&SPIRVDecompiler::Assign,
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&SPIRVDecompiler::Ternary<&Module::OpSelect, Type::Float, Type::Bool, Type::Float,
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&SPIRVDecompiler::Ternary<&Module::OpSelect, Type::Float, Type::Bool, Type::Float,
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@ -1291,8 +1282,7 @@ private:
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&SPIRVDecompiler::Binary<&Module::OpLogicalNotEqual, Type::Bool>,
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&SPIRVDecompiler::Binary<&Module::OpLogicalNotEqual, Type::Bool>,
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&SPIRVDecompiler::Unary<&Module::OpLogicalNot, Type::Bool>,
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&SPIRVDecompiler::Unary<&Module::OpLogicalNot, Type::Bool>,
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&SPIRVDecompiler::LogicalPick2,
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&SPIRVDecompiler::LogicalPick2,
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&SPIRVDecompiler::LogicalAll2,
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&SPIRVDecompiler::LogicalAnd2,
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&SPIRVDecompiler::LogicalAny2,
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&SPIRVDecompiler::Binary<&Module::OpFOrdLessThan, Type::Bool, Type::Float>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdLessThan, Type::Bool, Type::Float>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdEqual, Type::Bool, Type::Float>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdEqual, Type::Bool, Type::Float>,
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@ -1357,6 +1347,7 @@ private:
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&SPIRVDecompiler::WorkGroupId<1>,
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&SPIRVDecompiler::WorkGroupId<1>,
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&SPIRVDecompiler::WorkGroupId<2>,
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&SPIRVDecompiler::WorkGroupId<2>,
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};
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};
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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const VKDevice& device;
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const VKDevice& device;
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const ShaderIR& ir;
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const ShaderIR& ir;
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@ -23,38 +23,51 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);
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Node op_b = [&]() {
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Tegra::Shader::PredCondition cond{};
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switch (opcode->get().GetId()) {
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bool h_and{};
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case OpCode::Id::HSETP2_R:
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Node op_b{};
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return GetOperandAbsNegHalf(GetRegister(instr.gpr20), instr.hsetp2.abs_a,
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switch (opcode->get().GetId()) {
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instr.hsetp2.negate_b);
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case OpCode::Id::HSETP2_C:
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default:
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cond = instr.hsetp2.cbuf_and_imm.cond;
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UNREACHABLE();
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h_and = instr.hsetp2.cbuf_and_imm.h_and;
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return Immediate(0);
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op_b = GetOperandAbsNegHalf(GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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}
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instr.hsetp2.cbuf.abs_b, instr.hsetp2.cbuf.negate_b);
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}();
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break;
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op_b = UnpackHalfFloat(op_b, instr.hsetp2.type_b);
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case OpCode::Id::HSETP2_IMM:
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cond = instr.hsetp2.cbuf_and_imm.cond;
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// We can't use the constant predicate as destination.
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h_and = instr.hsetp2.cbuf_and_imm.h_and;
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ASSERT(instr.hsetp2.pred3 != static_cast<u64>(Pred::UnusedIndex));
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op_b = UnpackHalfImmediate(instr, true);
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break;
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const Node second_pred = GetPredicate(instr.hsetp2.pred39, instr.hsetp2.neg_pred != 0);
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case OpCode::Id::HSETP2_R:
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cond = instr.hsetp2.reg.cond;
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h_and = instr.hsetp2.reg.h_and;
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op_b =
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UnpackHalfFloat(GetOperandAbsNegHalf(GetRegister(instr.gpr20), instr.hsetp2.reg.abs_b,
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instr.hsetp2.reg.negate_b),
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instr.hsetp2.reg.type_b);
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break;
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default:
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UNREACHABLE();
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op_b = Immediate(0);
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}
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const OperationCode combiner = GetPredicateCombiner(instr.hsetp2.op);
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const OperationCode combiner = GetPredicateCombiner(instr.hsetp2.op);
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const OperationCode pair_combiner =
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const Node pred39 = GetPredicate(instr.hsetp2.pred39, instr.hsetp2.neg_pred);
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instr.hsetp2.h_and ? OperationCode::LogicalAll2 : OperationCode::LogicalAny2;
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const Node comparison = GetPredicateComparisonHalf(instr.hsetp2.cond, op_a, op_b);
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const auto Write = [&](u64 dest, Node src) {
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const Node first_pred = Operation(pair_combiner, comparison);
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SetPredicate(bb, dest, Operation(combiner, std::move(src), pred39));
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};
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// Set the primary predicate to the result of Predicate OP SecondPredicate
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const Node comparison = GetPredicateComparisonHalf(cond, op_a, op_b);
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const Node value = Operation(combiner, first_pred, second_pred);
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const u64 first = instr.hsetp2.pred0;
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SetPredicate(bb, instr.hsetp2.pred3, value);
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const u64 second = instr.hsetp2.pred3;
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if (h_and) {
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if (instr.hsetp2.pred0 != static_cast<u64>(Pred::UnusedIndex)) {
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const Node joined = Operation(OperationCode::LogicalAnd2, comparison);
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// Set the secondary predicate to the result of !Predicate OP SecondPredicate, if enabled
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Write(first, joined);
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const Node negated_pred = Operation(OperationCode::LogicalNegate, first_pred);
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Write(second, Operation(OperationCode::LogicalNegate, joined));
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SetPredicate(bb, instr.hsetp2.pred0, Operation(combiner, negated_pred, second_pred));
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} else {
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Write(first, Operation(OperationCode::LogicalPick2, comparison, Immediate(0u)));
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Write(second, Operation(OperationCode::LogicalPick2, comparison, Immediate(1u)));
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}
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}
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return pc;
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return pc;
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@ -101,8 +101,7 @@ enum class OperationCode {
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LogicalXor, /// (bool a, bool b) -> bool
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LogicalXor, /// (bool a, bool b) -> bool
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LogicalNegate, /// (bool a) -> bool
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LogicalNegate, /// (bool a) -> bool
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LogicalPick2, /// (bool2 pair, uint index) -> bool
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LogicalPick2, /// (bool2 pair, uint index) -> bool
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LogicalAll2, /// (bool2 a) -> bool
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LogicalAnd2, /// (bool2 a) -> bool
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LogicalAny2, /// (bool2 a) -> bool
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LogicalFLessThan, /// (float a, float b) -> bool
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LogicalFLessThan, /// (float a, float b) -> bool
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LogicalFEqual, /// (float a, float b) -> bool
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LogicalFEqual, /// (float a, float b) -> bool
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