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Merge pull request #774 from lioncash/decodings 

dyncom: Add ARMv6K NOP and hint instructions to the interpreter.
This commit is contained in:
Yuri Kunde Schlesner 2015-05-15 11:36:20 -07:00
parent 6abed88092 8cd72428c9
commit 12f6216741
2 changed files with 191 additions and 33 deletions
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28
src/core/arm/dyncom/arm_dyncom_dec.cpp
View File

@ -181,7 +181,11 @@ const ISEITEM arm_instruction[] = {
{ "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 }, { "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 },
{ "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 }, { "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 },
{ "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 }, { "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 },
{ "msr", 2, 0, 23, 27, 0x00000006, 20, 21, 0x00000002 }, { "msr", 3, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000001 },
{ "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 19, 0x00000004 },
{ "msr", 5, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 19, 19, 0x00000001, 16, 17, 0x00000000 },
{ "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 17, 0x00000001 },
{ "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 17, 17, 0x00000001 },
{ "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 }, { "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 },
{ "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 }, { "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 },
{ "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 }, { "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 },
@ -190,12 +194,17 @@ const ISEITEM arm_instruction[] = {
{ "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 }, { "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 },
{ "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 }, { "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 },
{ "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 }, { "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 },
{ "swi", 1, 0, 24, 27, 0x0000000f },
{ "bbl", 1, 0, 25, 27, 0x00000005 },
{ "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 }, { "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 },
{ "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 }, { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 },
{ "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 }, { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 },
{ "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 }, { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 },
{ "nop", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000000 },
{ "yield", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000001 },
{ "wfe", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000002 },
{ "wfi", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000003 },
{ "sev", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000004 },
{ "swi", 1, 0, 24, 27, 0x0000000f },
{ "bbl", 1, 0, 25, 27, 0x00000005 },
}; };
const ISEITEM arm_exclusion_code[] = { const ISEITEM arm_exclusion_code[] = {
@ -375,6 +384,10 @@ const ISEITEM arm_exclusion_code[] = {
{ "mrc", 0, 6, 0 }, { "mrc", 0, 6, 0 },
{ "mcr", 0, 0, 0 }, { "mcr", 0, 0, 0 },
{ "msr", 0, 0, 0 }, { "msr", 0, 0, 0 },
{ "msr", 0, 0, 0 },
{ "msr", 0, 0, 0 },
{ "msr", 0, 0, 0 },
{ "msr", 0, 0, 0 },
{ "ldrb", 0, 0, 0 }, { "ldrb", 0, 0, 0 },
{ "strb", 0, 0, 0 }, { "strb", 0, 0, 0 },
{ "ldr", 0, 0, 0 }, { "ldr", 0, 0, 0 },
@ -383,12 +396,17 @@ const ISEITEM arm_exclusion_code[] = {
{ "cdp", 0, 0, 0 }, { "cdp", 0, 0, 0 },
{ "stc", 0, 0, 0 }, { "stc", 0, 0, 0 },
{ "ldc", 0, 0, 0 }, { "ldc", 0, 0, 0 },
{ "swi", 0, 0, 0 },
{ "bbl", 0, 0, 0 },
{ "ldrexd", 0, ARMV6K, 0 }, { "ldrexd", 0, ARMV6K, 0 },
{ "strexd", 0, ARMV6K, 0 }, { "strexd", 0, ARMV6K, 0 },
{ "ldrexh", 0, ARMV6K, 0 }, { "ldrexh", 0, ARMV6K, 0 },
{ "strexh", 0, ARMV6K, 0 }, { "strexh", 0, ARMV6K, 0 },
{ "nop", 0, ARMV6K, 0 },
{ "yield", 0, ARMV6K, 0 },
{ "wfe", 0, ARMV6K, 0 },
{ "wfi", 0, ARMV6K, 0 },
{ "sev", 0, ARMV6K, 0 },
{ "swi", 0, 0, 0 },
{ "bbl", 0, 0, 0 },
{ "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4] { "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4]
{ "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3] { "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3]

194
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View File

@ -2037,6 +2037,19 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index)
return inst_base; return inst_base;
} }
// NOP introduced in ARMv6K.
static ARM_INST_PTR INTERPRETER_TRANSLATE(nop)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
inst_base->cond = BITS(inst, 28, 31);
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index)
{ {
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst)); arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst));
@ -2328,6 +2341,18 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index)
return inst_base; return inst_base;
} }
static ARM_INST_PTR INTERPRETER_TRANSLATE(sev)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
inst_base->cond = BITS(inst, 28, 31);
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index)
{ {
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
@ -3332,6 +3357,40 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index)
return INTERPRETER_TRANSLATE(uxtab16)(inst, index); return INTERPRETER_TRANSLATE(uxtab16)(inst, index);
} }
static ARM_INST_PTR INTERPRETER_TRANSLATE(wfe)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
inst_base->cond = BITS(inst, 28, 31);
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(wfi)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
inst_base->cond = BITS(inst, 28, 31);
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
inst_base->cond = BITS(inst, 28, 31);
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
return inst_base;
}
// Floating point VFPv3 structures and instructions // Floating point VFPv3 structures and instructions
#define VFP_INTERPRETER_STRUCT #define VFP_INTERPRETER_STRUCT
@ -3521,6 +3580,10 @@ const transop_fp_t arm_instruction_trans[] = {
INTERPRETER_TRANSLATE(mrc), INTERPRETER_TRANSLATE(mrc),
INTERPRETER_TRANSLATE(mcr), INTERPRETER_TRANSLATE(mcr),
INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(msr),
INTERPRETER_TRANSLATE(msr),
INTERPRETER_TRANSLATE(msr),
INTERPRETER_TRANSLATE(msr),
INTERPRETER_TRANSLATE(msr),
INTERPRETER_TRANSLATE(ldrb), INTERPRETER_TRANSLATE(ldrb),
INTERPRETER_TRANSLATE(strb), INTERPRETER_TRANSLATE(strb),
INTERPRETER_TRANSLATE(ldr), INTERPRETER_TRANSLATE(ldr),
@ -3529,12 +3592,17 @@ const transop_fp_t arm_instruction_trans[] = {
INTERPRETER_TRANSLATE(cdp), INTERPRETER_TRANSLATE(cdp),
INTERPRETER_TRANSLATE(stc), INTERPRETER_TRANSLATE(stc),
INTERPRETER_TRANSLATE(ldc), INTERPRETER_TRANSLATE(ldc),
INTERPRETER_TRANSLATE(swi),
INTERPRETER_TRANSLATE(bbl),
INTERPRETER_TRANSLATE(ldrexd), INTERPRETER_TRANSLATE(ldrexd),
INTERPRETER_TRANSLATE(strexd), INTERPRETER_TRANSLATE(strexd),
INTERPRETER_TRANSLATE(ldrexh), INTERPRETER_TRANSLATE(ldrexh),
INTERPRETER_TRANSLATE(strexh), INTERPRETER_TRANSLATE(strexh),
INTERPRETER_TRANSLATE(nop),
INTERPRETER_TRANSLATE(yield),
INTERPRETER_TRANSLATE(wfe),
INTERPRETER_TRANSLATE(wfi),
INTERPRETER_TRANSLATE(sev),
INTERPRETER_TRANSLATE(swi),
INTERPRETER_TRANSLATE(bbl),
// All the thumb instructions should be placed the end of table // All the thumb instructions should be placed the end of table
INTERPRETER_TRANSLATE(b_2_thumb), INTERPRETER_TRANSLATE(b_2_thumb),
@ -3709,6 +3777,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
inst_base = (arm_inst *)&inst_buf[ptr] inst_base = (arm_inst *)&inst_buf[ptr]
#define INC_PC(l) ptr += sizeof(arm_inst) + l #define INC_PC(l) ptr += sizeof(arm_inst) + l
#define INC_PC_STUB ptr += sizeof(arm_inst)
// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
// clunky switch statement. // clunky switch statement.
@ -3897,28 +3966,37 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
case 172: goto MRC_INST; \ case 172: goto MRC_INST; \
case 173: goto MCR_INST; \ case 173: goto MCR_INST; \
case 174: goto MSR_INST; \ case 174: goto MSR_INST; \
case 175: goto LDRB_INST; \ case 175: goto MSR_INST; \
case 176: goto STRB_INST; \ case 176: goto MSR_INST; \
case 177: goto LDR_INST; \ case 177: goto MSR_INST; \
case 178: goto LDRCOND_INST ; \ case 178: goto MSR_INST; \
case 179: goto STR_INST; \ case 179: goto LDRB_INST; \
case 180: goto CDP_INST; \ case 180: goto STRB_INST; \
case 181: goto STC_INST; \ case 181: goto LDR_INST; \
case 182: goto LDC_INST; \ case 182: goto LDRCOND_INST ; \
case 183: goto SWI_INST; \ case 183: goto STR_INST; \
case 184: goto BBL_INST; \ case 184: goto CDP_INST; \
case 185: goto LDREXD_INST; \ case 185: goto STC_INST; \
case 186: goto STREXD_INST; \ case 186: goto LDC_INST; \
case 187: goto LDREXH_INST; \ case 187: goto LDREXD_INST; \
case 188: goto STREXH_INST; \ case 188: goto STREXD_INST; \
case 189: goto B_2_THUMB ; \ case 189: goto LDREXH_INST; \
case 190: goto B_COND_THUMB ; \ case 190: goto STREXH_INST; \
case 191: goto BL_1_THUMB ; \ case 191: goto NOP_INST; \
case 192: goto BL_2_THUMB ; \ case 192: goto YIELD_INST; \
case 193: goto BLX_1_THUMB ; \ case 193: goto WFE_INST; \
case 194: goto DISPATCH; \ case 194: goto WFI_INST; \
case 195: goto INIT_INST_LENGTH; \ case 195: goto SEV_INST; \
case 196: goto END; \ case 196: goto SWI_INST; \
case 197: goto BBL_INST; \
case 198: goto B_2_THUMB ; \
case 199: goto B_COND_THUMB ; \
case 200: goto BL_1_THUMB ; \
case 201: goto BL_2_THUMB ; \
case 202: goto BLX_1_THUMB ; \
case 203: goto DISPATCH; \
case 204: goto INIT_INST_LENGTH; \
case 205: goto END; \
} }
#endif #endif
@ -3964,9 +4042,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
&&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST, &&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST,
&&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST,
&&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST,
&&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST, &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,
&&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST,
&&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST,
&&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&NOP_INST, &&YIELD_INST, &&WFE_INST, &&WFI_INST, &&SEV_INST, &&SWI_INST,&&BBL_INST,
&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
&&INIT_INST_LENGTH,&&END &&INIT_INST_LENGTH,&&END
}; };
#endif #endif
@ -5019,6 +5099,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
GOTO_NEXT_INST; GOTO_NEXT_INST;
} }
NOP_INST:
{
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC_STUB;
FETCH_INST;
GOTO_NEXT_INST;
}
PKHBT_INST: PKHBT_INST:
{ {
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
@ -5502,6 +5590,19 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
GOTO_NEXT_INST; GOTO_NEXT_INST;
} }
SEV_INST:
{
// Stubbed, as SEV is a hint instruction.
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "SEV executed.");
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC_STUB;
FETCH_INST;
GOTO_NEXT_INST;
}
SHADD8_INST: SHADD8_INST:
SHADD16_INST: SHADD16_INST:
SHADDSUBX_INST: SHADDSUBX_INST:
@ -6965,6 +7066,45 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
GOTO_NEXT_INST; GOTO_NEXT_INST;
} }
WFE_INST:
{
// Stubbed, as WFE is a hint instruction.
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "WFE executed.");
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC_STUB;
FETCH_INST;
GOTO_NEXT_INST;
}
WFI_INST:
{
// Stubbed, as WFI is a hint instruction.
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "WFI executed.");
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC_STUB;
FETCH_INST;
GOTO_NEXT_INST;
}
YIELD_INST:
{
// Stubbed, as YIELD is a hint instruction.
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "YIELD executed.");
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC_STUB;
FETCH_INST;
GOTO_NEXT_INST;
}
#define VFP_INTERPRETER_IMPL #define VFP_INTERPRETER_IMPL
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp" #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_INTERPRETER_IMPL #undef VFP_INTERPRETER_IMPL