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arm: Use 64-bit addressing in a bunch of places.

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This commit is contained in:
bunnei 2017-08-28 21:09:42 -04:00
parent 1c4f9e822c
commit 3411883fe3
9 changed files with 113 additions and 80 deletions
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4
src/common/common_types.h
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@ -47,8 +47,8 @@ typedef double f64; ///< 64-bit floating point
// TODO: It would be nice to eventually replace these with strong types that prevent accidental
// conversion between each other.
typedef u32 VAddr; ///< Represents a pointer in the userspace virtual address space.
typedef u32 PAddr; ///< Represents a pointer in the ARM11 physical address space.
typedef u64 VAddr; ///< Represents a pointer in the userspace virtual address space.
typedef u64 PAddr; ///< Represents a pointer in the ARM11 physical address space.
// An inheritable class to disallow the copy constructor and operator= functions
class NonCopyable {

28
src/core/arm/arm_interface.h
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@ -14,14 +14,14 @@ public:
virtual ~ARM_Interface() {}
struct ThreadContext {
u32 cpu_registers[13];
u32 sp;
u32 lr;
u32 pc;
u32 cpsr;
u32 fpu_registers[64];
u32 fpscr;
u32 fpexc;
u64 cpu_registers[30];
u64 lr;
u64 sp;
u64 pc;
u64 cpsr;
u64 fpu_registers[64];
u64 fpscr;
u64 fpexc;
};
/**
@ -45,27 +45,27 @@ public:
* Set the Program Counter to an address
* @param addr Address to set PC to
*/
virtual void SetPC(u32 addr) = 0;
virtual void SetPC(u64 addr) = 0;
/*
* Get the current Program Counter
* @return Returns current PC
*/
virtual u32 GetPC() const = 0;
virtual u64 GetPC() const = 0;
/**
* Get an ARM register
* @param index Register index (0-15)
* @param index Register index
* @return Returns the value in the register
*/
virtual u32 GetReg(int index) const = 0;
virtual u64 GetReg(int index) const = 0;
/**
* Set an ARM register
* @param index Register index (0-15)
* @param index Register index
* @param value Value to set register to
*/
virtual void SetReg(int index, u32 value) = 0;
virtual void SetReg(int index, u64 value) = 0;
/**
* Gets the value of a VFP register

129
src/core/arm/dynarmic/arm_dynarmic.cpp
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@ -14,72 +14,105 @@
#include "core/hle/svc.h"
#include "core/memory.h"
static void InterpreterFallback(u32 pc, Dynarmic::Jit* jit, void* user_arg) {
ARMul_State* state = static_cast<ARMul_State*>(user_arg);
static void InterpreterFallback(u64 pc, Dynarmic::Jit* jit, void* user_arg) {
UNIMPLEMENTED_MSG("InterpreterFallback for ARM64 JIT does not exist!");
//ARMul_State* state = static_cast<ARMul_State*>(user_arg);
state->Reg = jit->Regs();
state->Cpsr = jit->Cpsr();
state->Reg[15] = pc;
state->ExtReg = jit->ExtRegs();
state->VFP[VFP_FPSCR] = jit->Fpscr();
state->NumInstrsToExecute = 1;
//state->Reg = jit->Regs();
//state->Cpsr = jit->Cpsr();
//state->Reg[15] = static_cast<u32>(pc);
//state->ExtReg = jit->ExtRegs();
//state->VFP[VFP_FPSCR] = jit->Fpscr();
//state->NumInstrsToExecute = 1;
InterpreterMainLoop(state);
//InterpreterMainLoop(state);
bool is_thumb = (state->Cpsr & (1 << 5)) != 0;
state->Reg[15] &= (is_thumb ? 0xFFFFFFFE : 0xFFFFFFFC);
//bool is_thumb = (state->Cpsr & (1 << 5)) != 0;
//state->Reg[15] &= (is_thumb ? 0xFFFFFFFE : 0xFFFFFFFC);
jit->Regs() = state->Reg;
jit->Cpsr() = state->Cpsr;
jit->ExtRegs() = state->ExtReg;
jit->SetFpscr(state->VFP[VFP_FPSCR]);
//jit->Regs() = state->Reg;
//jit->Cpsr() = state->Cpsr;
//jit->ExtRegs() = state->ExtReg;
//jit->SetFpscr(state->VFP[VFP_FPSCR]);
}
static bool IsReadOnlyMemory(u32 vaddr) {
static bool IsReadOnlyMemory(u64 vaddr) {
// TODO(bunnei): ImplementMe
return false;
}
u8 MemoryRead8(const u64 addr) {
return Memory::Read8(static_cast<VAddr>(addr));
}
u16 MemoryRead16(const u64 addr) {
return Memory::Read16(static_cast<VAddr>(addr));
}
u32 MemoryRead32(const u64 addr) {
return Memory::Read32(static_cast<VAddr>(addr));
}
u64 MemoryRead64(const u64 addr) {
return Memory::Read64(static_cast<VAddr>(addr));
}
void MemoryWrite8(const u64 addr, const u8 data) {
Memory::Write8(static_cast<VAddr>(addr), data);
}
void MemoryWrite16(const u64 addr, const u16 data) {
Memory::Write16(static_cast<VAddr>(addr), data);
}
void MemoryWrite32(const u64 addr, const u32 data) {
Memory::Write32(static_cast<VAddr>(addr), data);
}
void MemoryWrite64(const u64 addr, const u64 data) {
Memory::Write64(static_cast<VAddr>(addr), data);
}
static Dynarmic::UserCallbacks GetUserCallbacks(
const std::shared_ptr<ARMul_State>& interpeter_state) {
Dynarmic::UserCallbacks user_callbacks{};
user_callbacks.InterpreterFallback = &InterpreterFallback;
user_callbacks.user_arg = static_cast<void*>(interpeter_state.get());
//user_callbacks.InterpreterFallback = &InterpreterFallback;
//user_callbacks.user_arg = static_cast<void*>(interpeter_state.get());
user_callbacks.CallSVC = &SVC::CallSVC;
user_callbacks.memory.IsReadOnlyMemory = &IsReadOnlyMemory;
user_callbacks.memory.ReadCode = &Memory::Read32;
user_callbacks.memory.Read8 = &Memory::Read8;
user_callbacks.memory.Read16 = &Memory::Read16;
user_callbacks.memory.Read32 = &Memory::Read32;
user_callbacks.memory.Read64 = &Memory::Read64;
user_callbacks.memory.Write8 = &Memory::Write8;
user_callbacks.memory.Write16 = &Memory::Write16;
user_callbacks.memory.Write32 = &Memory::Write32;
user_callbacks.memory.Write64 = &Memory::Write64;
user_callbacks.page_table = Memory::GetCurrentPageTablePointers();
user_callbacks.memory.ReadCode = &MemoryRead32;
user_callbacks.memory.Read8 = &MemoryRead8;
user_callbacks.memory.Read16 = &MemoryRead16;
user_callbacks.memory.Read32 = &MemoryRead32;
user_callbacks.memory.Read64 = &MemoryRead64;
user_callbacks.memory.Write8 = &MemoryWrite8;
user_callbacks.memory.Write16 = &MemoryWrite16;
user_callbacks.memory.Write32 = &MemoryWrite32;
user_callbacks.memory.Write64 = &MemoryWrite64;
//user_callbacks.page_table = Memory::GetCurrentPageTablePointers();
user_callbacks.coprocessors[15] = std::make_shared<DynarmicCP15>(interpeter_state);
return user_callbacks;
}
ARM_Dynarmic::ARM_Dynarmic(PrivilegeMode initial_mode) {
interpreter_state = std::make_shared<ARMul_State>(initial_mode);
jit = std::make_unique<Dynarmic::Jit>(GetUserCallbacks(interpreter_state));
jit = std::make_unique<Dynarmic::Jit>(GetUserCallbacks(interpreter_state), Dynarmic::Arch::ARM64);
}
void ARM_Dynarmic::SetPC(u32 pc) {
jit->Regs()[15] = pc;
void ARM_Dynarmic::SetPC(u64 pc) {
jit->Regs64()[32] = pc;
}
u32 ARM_Dynarmic::GetPC() const {
return jit->Regs()[15];
u64 ARM_Dynarmic::GetPC() const {
return jit->Regs64()[32];
}
u32 ARM_Dynarmic::GetReg(int index) const {
return jit->Regs()[index];
u64 ARM_Dynarmic::GetReg(int index) const {
return jit->Regs64()[index];
}
void ARM_Dynarmic::SetReg(int index, u32 value) {
jit->Regs()[index] = value;
void ARM_Dynarmic::SetReg(int index, u64 value) {
jit->Regs64()[index] = value;
}
u32 ARM_Dynarmic::GetVFPReg(int index) const {
@ -136,18 +169,18 @@ MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
MICROPROFILE_SCOPE(ARM_Jit);
unsigned ticks_executed = jit->Run(static_cast<unsigned>(num_instructions));
unsigned ticks_executed = jit->Run(1 /*static_cast<unsigned>(num_instructions)*/);
AddTicks(ticks_executed);
}
void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
memcpy(ctx.cpu_registers, jit->Regs().data(), sizeof(ctx.cpu_registers));
memcpy(ctx.fpu_registers, jit->ExtRegs().data(), sizeof(ctx.fpu_registers));
memcpy(ctx.cpu_registers, jit->Regs64().data(), sizeof(ctx.cpu_registers));
//memcpy(ctx.fpu_registers, jit->ExtRegs().data(), sizeof(ctx.fpu_registers));
ctx.sp = jit->Regs()[13];
ctx.lr = jit->Regs()[14];
ctx.pc = jit->Regs()[15];
ctx.lr = jit->Regs64()[30];
ctx.sp = jit->Regs64()[31];
ctx.pc = jit->Regs64()[32];
ctx.cpsr = jit->Cpsr();
ctx.fpscr = jit->Fpscr();
@ -155,12 +188,12 @@ void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
}
void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
memcpy(jit->Regs().data(), ctx.cpu_registers, sizeof(ctx.cpu_registers));
memcpy(jit->ExtRegs().data(), ctx.fpu_registers, sizeof(ctx.fpu_registers));
memcpy(jit->Regs64().data(), ctx.cpu_registers, sizeof(ctx.cpu_registers));
//memcpy(jit->ExtRegs().data(), ctx.fpu_registers, sizeof(ctx.fpu_registers));
jit->Regs()[13] = ctx.sp;
jit->Regs()[14] = ctx.lr;
jit->Regs()[15] = ctx.pc;
jit->Regs64()[30] = ctx.lr;
jit->Regs64()[31] = ctx.sp;
jit->Regs64()[32] = ctx.pc;
jit->Cpsr() = ctx.cpsr;
jit->SetFpscr(ctx.fpscr);

8
src/core/arm/dynarmic/arm_dynarmic.h
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@ -14,10 +14,10 @@ class ARM_Dynarmic final : public ARM_Interface {
public:
ARM_Dynarmic(PrivilegeMode initial_mode);
void SetPC(u32 pc) override;
u32 GetPC() const override;
u32 GetReg(int index) const override;
void SetReg(int index, u32 value) override;
void SetPC(u64 pc) override;
u64 GetPC() const override;
u64 GetReg(int index) const override;
void SetReg(int index, u64 value) override;
u32 GetVFPReg(int index) const override;
void SetVFPReg(int index, u32 value) override;
u32 GetVFPSystemReg(VFPSystemRegister reg) const override;

8
src/core/arm/dyncom/arm_dyncom.cpp
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@ -25,19 +25,19 @@ void ARM_DynCom::ClearInstructionCache() {
trans_cache_buf_top = 0;
}
void ARM_DynCom::SetPC(u32 pc) {
void ARM_DynCom::SetPC(u64 pc) {
state->Reg[15] = pc;
}
u32 ARM_DynCom::GetPC() const {
u64 ARM_DynCom::GetPC() const {
return state->Reg[15];
}
u32 ARM_DynCom::GetReg(int index) const {
u64 ARM_DynCom::GetReg(int index) const {
return state->Reg[index];
}
void ARM_DynCom::SetReg(int index, u32 value) {
void ARM_DynCom::SetReg(int index, u64 value) {
state->Reg[index] = value;
}

8
src/core/arm/dyncom/arm_dyncom.h
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@ -17,10 +17,10 @@ public:
void ClearInstructionCache() override;
void SetPC(u32 pc) override;
u32 GetPC() const override;
u32 GetReg(int index) const override;
void SetReg(int index, u32 value) override;
void SetPC(u64 pc) override;
u64 GetPC() const override;
u64 GetReg(int index) const override;
void SetReg(int index, u64 value) override;
u32 GetVFPReg(int index) const override;
void SetVFPReg(int index, u32 value) override;
u32 GetVFPSystemReg(VFPSystemRegister reg) const override;

4
src/core/gdbstub/gdbstub.h
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@ -69,7 +69,7 @@ void HandlePacket();
* @param addr Address to search from.
* @param type Type of breakpoint.
*/
BreakpointAddress GetNextBreakpointFromAddress(u32 addr, GDBStub::BreakpointType type);
BreakpointAddress GetNextBreakpointFromAddress(PAddr addr, GDBStub::BreakpointType type);
/**
* Check if a breakpoint of the specified type exists at the given address.
@ -77,7 +77,7 @@ BreakpointAddress GetNextBreakpointFromAddress(u32 addr, GDBStub::BreakpointType
* @param addr Address of breakpoint.
* @param type Type of breakpoint.
*/
bool CheckBreakpoint(u32 addr, GDBStub::BreakpointType type);
bool CheckBreakpoint(PAddr addr, GDBStub::BreakpointType type);
// If set to true, the CPU will halt at the beginning of the next CPU loop.
bool GetCpuHaltFlag();

2
src/core/hle/function_wrappers.h
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@ -20,7 +20,7 @@ namespace HLE {
* HLE a function return from the current ARM11 userland process
* @param res Result to return
*/
static inline void FuncReturn(u32 res) {
static inline void FuncReturn(u64 res) {
Core::CPU().SetReg(0, res);
}

2
src/core/hle/service/ldr_ro/cro_helper.cpp
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@ -274,7 +274,7 @@ ResultVal<VAddr> CROHelper::RebaseSegmentTable(u32 cro_size, VAddr data_segment_
}
SetEntry(i, segment);
}
return MakeResult<u32>(prev_data_segment + module_address);
return MakeResult<VAddr>(prev_data_segment + module_address);
}
ResultCode CROHelper::RebaseExportNamedSymbolTable() {