diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 67501cf0a..d3095089c 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -563,6 +563,10 @@ union Instruction {
         BitField<48, 1, u64> negate_b;
     } fmul;
 
+    union {
+        BitField<55, 1, u64> saturate;
+    } fmul32;
+
     union {
         BitField<48, 1, u64> is_signed;
     } shift;
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 09db58ab6..a3daef014 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -1460,9 +1460,10 @@ private:
                 break;
             }
             case OpCode::Id::FMUL32_IMM: {
-                regs.SetRegisterToFloat(
-                    instr.gpr0, 0,
-                    regs.GetRegisterAsFloat(instr.gpr8) + " * " + GetImmediate32(instr), 1, 1);
+                regs.SetRegisterToFloat(instr.gpr0, 0,
+                                        regs.GetRegisterAsFloat(instr.gpr8) + " * " +
+                                            GetImmediate32(instr),
+                                        1, 1, instr.fmul32.saturate);
                 break;
             }
             case OpCode::Id::FADD32I: {