buffer_cache: Reduce uniform buffer size from shader usage
Increases performance significantly on certain titles.
This commit is contained in:
parent
e57ee3b7fd
commit
4a2361a1e2
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@ -560,32 +560,45 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::GetCbufU32:
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case IR::Opcode::GetCbufF32:
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case IR::Opcode::GetCbufU32x2: {
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if (const IR::Value index{inst.Arg(0)}; index.IsImmediate()) {
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AddConstantBufferDescriptor(info, index.U32(), 1);
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} else {
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const IR::Value index{inst.Arg(0)};
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const IR::Value offset{inst.Arg(1)};
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if (!index.IsImmediate()) {
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throw NotImplementedException("Constant buffer with non-immediate index");
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}
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AddConstantBufferDescriptor(info, index.U32(), 1);
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u32 element_size{};
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switch (inst.GetOpcode()) {
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case IR::Opcode::GetCbufU8:
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case IR::Opcode::GetCbufS8:
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info.used_constant_buffer_types |= IR::Type::U8;
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element_size = 1;
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break;
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case IR::Opcode::GetCbufU16:
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case IR::Opcode::GetCbufS16:
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info.used_constant_buffer_types |= IR::Type::U16;
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element_size = 2;
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break;
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case IR::Opcode::GetCbufU32:
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info.used_constant_buffer_types |= IR::Type::U32;
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element_size = 4;
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break;
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case IR::Opcode::GetCbufF32:
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info.used_constant_buffer_types |= IR::Type::F32;
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element_size = 4;
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break;
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case IR::Opcode::GetCbufU32x2:
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info.used_constant_buffer_types |= IR::Type::U32x2;
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element_size = 8;
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break;
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default:
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break;
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}
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u32& size{info.constant_buffer_used_sizes[index.U32()]};
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if (offset.IsImmediate()) {
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size = std::max(size, offset.U32() + element_size);
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} else {
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size = 0x10'000;
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}
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break;
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}
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case IR::Opcode::BindlessImageSampleImplicitLod:
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@ -197,6 +197,7 @@ struct Info {
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IR::Type used_storage_buffer_types{};
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u32 constant_buffer_mask{};
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std::array<u32, MAX_CBUFS> constant_buffer_used_sizes{};
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u32 nvn_buffer_base{};
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std::bitset<16> nvn_buffer_used{};
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@ -44,6 +44,7 @@ MICROPROFILE_DECLARE(GPU_DownloadMemory);
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using BufferId = SlotId;
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using VideoCore::Surface::PixelFormat;
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using namespace Common::Literals;
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constexpr u32 NUM_VERTEX_BUFFERS = 32;
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constexpr u32 NUM_TRANSFORM_FEEDBACK_BUFFERS = 4;
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@ -53,7 +54,8 @@ constexpr u32 NUM_STORAGE_BUFFERS = 16;
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constexpr u32 NUM_TEXTURE_BUFFERS = 16;
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constexpr u32 NUM_STAGES = 5;
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using namespace Common::Literals;
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using UniformBufferSizes = std::array<std::array<u32, NUM_GRAPHICS_UNIFORM_BUFFERS>, NUM_STAGES>;
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using ComputeUniformBufferSizes = std::array<u32, NUM_COMPUTE_UNIFORM_BUFFERS>;
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template <typename P>
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class BufferCache {
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@ -142,9 +144,10 @@ public:
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void BindHostComputeBuffers();
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void SetEnabledUniformBuffers(const std::array<u32, NUM_STAGES>& mask);
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void SetUniformBuffersState(const std::array<u32, NUM_STAGES>& mask,
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const UniformBufferSizes* sizes);
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void SetEnabledComputeUniformBuffers(u32 enabled);
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void SetComputeUniformBufferState(u32 mask, const ComputeUniformBufferSizes* sizes);
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void UnbindGraphicsStorageBuffers(size_t stage);
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@ -384,8 +387,11 @@ private:
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std::array<Binding, NUM_STORAGE_BUFFERS> compute_storage_buffers;
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std::array<TextureBufferBinding, NUM_TEXTURE_BUFFERS> compute_texture_buffers;
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std::array<u32, NUM_STAGES> enabled_uniform_buffers{};
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u32 enabled_compute_uniform_buffers = 0;
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std::array<u32, NUM_STAGES> enabled_uniform_buffer_masks{};
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u32 enabled_compute_uniform_buffer_mask = 0;
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const UniformBufferSizes* uniform_buffer_sizes{};
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const ComputeUniformBufferSizes* compute_uniform_buffer_sizes{};
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std::array<u32, NUM_STAGES> enabled_storage_buffers{};
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std::array<u32, NUM_STAGES> written_storage_buffers{};
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@ -670,18 +676,22 @@ void BufferCache<P>::BindHostComputeBuffers() {
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}
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template <class P>
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void BufferCache<P>::SetEnabledUniformBuffers(const std::array<u32, NUM_STAGES>& mask) {
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void BufferCache<P>::SetUniformBuffersState(const std::array<u32, NUM_STAGES>& mask,
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const UniformBufferSizes* sizes) {
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if constexpr (HAS_PERSISTENT_UNIFORM_BUFFER_BINDINGS) {
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if (enabled_uniform_buffers != mask) {
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if (enabled_uniform_buffer_masks != mask) {
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dirty_uniform_buffers.fill(~u32{0});
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}
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}
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enabled_uniform_buffers = mask;
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enabled_uniform_buffer_masks = mask;
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uniform_buffer_sizes = sizes;
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}
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template <class P>
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void BufferCache<P>::SetEnabledComputeUniformBuffers(u32 enabled) {
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enabled_compute_uniform_buffers = enabled;
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void BufferCache<P>::SetComputeUniformBufferState(u32 mask,
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const ComputeUniformBufferSizes* sizes) {
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enabled_compute_uniform_buffer_mask = mask;
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compute_uniform_buffer_sizes = sizes;
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}
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template <class P>
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@ -984,7 +994,7 @@ void BufferCache<P>::BindHostGraphicsUniformBuffers(size_t stage) {
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dirty = std::exchange(dirty_uniform_buffers[stage], 0);
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}
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u32 binding_index = 0;
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ForEachEnabledBit(enabled_uniform_buffers[stage], [&](u32 index) {
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ForEachEnabledBit(enabled_uniform_buffer_masks[stage], [&](u32 index) {
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const bool needs_bind = ((dirty >> index) & 1) != 0;
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BindHostGraphicsUniformBuffer(stage, index, binding_index, needs_bind);
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if constexpr (NEEDS_BIND_UNIFORM_INDEX) {
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@ -998,7 +1008,7 @@ void BufferCache<P>::BindHostGraphicsUniformBuffer(size_t stage, u32 index, u32
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bool needs_bind) {
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const Binding& binding = uniform_buffers[stage][index];
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const VAddr cpu_addr = binding.cpu_addr;
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const u32 size = binding.size;
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const u32 size = std::min(binding.size, (*uniform_buffer_sizes)[stage][index]);
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Buffer& buffer = slot_buffers[binding.buffer_id];
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TouchBuffer(buffer);
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const bool use_fast_buffer = binding.buffer_id != NULL_BUFFER_ID &&
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@ -1113,11 +1123,11 @@ void BufferCache<P>::BindHostComputeUniformBuffers() {
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dirty_uniform_buffers.fill(~u32{0});
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}
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u32 binding_index = 0;
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ForEachEnabledBit(enabled_compute_uniform_buffers, [&](u32 index) {
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ForEachEnabledBit(enabled_compute_uniform_buffer_mask, [&](u32 index) {
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const Binding& binding = compute_uniform_buffers[index];
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Buffer& buffer = slot_buffers[binding.buffer_id];
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TouchBuffer(buffer);
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const u32 size = binding.size;
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const u32 size = std::min(binding.size, (*compute_uniform_buffer_sizes)[index]);
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SynchronizeBuffer(buffer, binding.cpu_addr, size);
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const u32 offset = buffer.Offset(binding.cpu_addr);
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@ -1261,7 +1271,7 @@ void BufferCache<P>::UpdateVertexBuffer(u32 index) {
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template <class P>
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void BufferCache<P>::UpdateUniformBuffers(size_t stage) {
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ForEachEnabledBit(enabled_uniform_buffers[stage], [&](u32 index) {
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ForEachEnabledBit(enabled_uniform_buffer_masks[stage], [&](u32 index) {
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Binding& binding = uniform_buffers[stage][index];
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if (binding.buffer_id) {
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// Already updated
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@ -1334,7 +1344,7 @@ void BufferCache<P>::UpdateTransformFeedbackBuffer(u32 index) {
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template <class P>
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void BufferCache<P>::UpdateComputeUniformBuffers() {
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ForEachEnabledBit(enabled_compute_uniform_buffers, [&](u32 index) {
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ForEachEnabledBit(enabled_compute_uniform_buffer_mask, [&](u32 index) {
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Binding& binding = compute_uniform_buffers[index];
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binding = NULL_BINDING;
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const auto& launch_desc = kepler_compute.launch_description;
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@ -43,6 +43,8 @@ ComputePipeline::ComputePipeline(const Device& device, TextureCache& texture_cac
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: texture_cache{texture_cache_}, buffer_cache{buffer_cache_}, gpu_memory{gpu_memory_},
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kepler_compute{kepler_compute_}, program_manager{program_manager_}, info{info_},
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source_program{std::move(source_program_)}, assembly_program{std::move(assembly_program_)} {
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std::copy_n(info.constant_buffer_used_sizes.begin(), uniform_buffer_sizes.size(),
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uniform_buffer_sizes.begin());
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num_texture_buffers = AccumulateCount(info.texture_buffer_descriptors);
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num_image_buffers = AccumulateCount(info.image_buffer_descriptors);
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@ -63,7 +65,7 @@ ComputePipeline::ComputePipeline(const Device& device, TextureCache& texture_cac
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}
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void ComputePipeline::Configure() {
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buffer_cache.SetEnabledComputeUniformBuffers(info.constant_buffer_mask);
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buffer_cache.SetComputeUniformBufferState(info.constant_buffer_mask, &uniform_buffer_sizes);
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buffer_cache.UnbindComputeStorageBuffers();
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size_t ssbo_index{};
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for (const auto& desc : info.storage_buffers_descriptors) {
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@ -72,6 +72,7 @@ private:
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Shader::Info info;
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OGLProgram source_program;
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OGLAssemblyProgram assembly_program;
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VideoCommon::ComputeUniformBufferSizes uniform_buffer_sizes{};
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u32 num_texture_buffers{};
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u32 num_image_buffers{};
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@ -60,6 +60,14 @@ std::pair<GLint, GLint> TransformFeedbackEnum(u8 location) {
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UNIMPLEMENTED_MSG("index={}", index);
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return {GL_POSITION, 0};
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}
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struct Spec {
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static constexpr std::array<bool, 5> enabled_stages{true, true, true, true, true};
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static constexpr bool has_storage_buffers = true;
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static constexpr bool has_texture_buffers = true;
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static constexpr bool has_image_buffers = true;
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static constexpr bool has_images = true;
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};
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} // Anonymous namespace
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size_t GraphicsPipelineKey::Hash() const noexcept {
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@ -100,7 +108,8 @@ GraphicsPipeline::GraphicsPipeline(const Device& device, TextureCache& texture_c
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base_uniform_bindings[stage + 1] += AccumulateCount(info.constant_buffer_descriptors);
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base_storage_bindings[stage + 1] += AccumulateCount(info.storage_buffers_descriptors);
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}
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enabled_uniform_buffers[stage] = info.constant_buffer_mask;
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enabled_uniform_buffer_masks[stage] = info.constant_buffer_mask;
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std::ranges::copy(info.constant_buffer_used_sizes, uniform_buffer_sizes[stage].begin());
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const u32 num_tex_buffer_bindings{AccumulateCount(info.texture_buffer_descriptors)};
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num_texture_buffers[stage] += num_tex_buffer_bindings;
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@ -130,14 +139,6 @@ GraphicsPipeline::GraphicsPipeline(const Device& device, TextureCache& texture_c
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}
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}
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struct Spec {
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static constexpr std::array<bool, 5> enabled_stages{true, true, true, true, true};
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static constexpr bool has_storage_buffers = true;
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static constexpr bool has_texture_buffers = true;
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static constexpr bool has_image_buffers = true;
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static constexpr bool has_images = true;
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};
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void GraphicsPipeline::Configure(bool is_indexed) {
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std::array<ImageId, MAX_TEXTURES + MAX_IMAGES> image_view_ids;
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std::array<u32, MAX_TEXTURES + MAX_IMAGES> image_view_indices;
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@ -147,7 +148,7 @@ void GraphicsPipeline::Configure(bool is_indexed) {
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texture_cache.SynchronizeGraphicsDescriptors();
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buffer_cache.SetEnabledUniformBuffers(enabled_uniform_buffers);
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buffer_cache.SetUniformBuffersState(enabled_uniform_buffer_masks, &uniform_buffer_sizes);
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buffer_cache.runtime.SetBaseUniformBindings(base_uniform_bindings);
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buffer_cache.runtime.SetBaseStorageBindings(base_storage_bindings);
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buffer_cache.runtime.SetEnableStorageBuffers(use_storage_buffers);
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@ -99,7 +99,8 @@ private:
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u32 enabled_stages_mask{};
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std::array<Shader::Info, 5> stage_infos{};
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std::array<u32, 5> enabled_uniform_buffers{};
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std::array<u32, 5> enabled_uniform_buffer_masks{};
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VideoCommon::UniformBufferSizes uniform_buffer_sizes{};
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std::array<u32, 5> base_uniform_bindings{};
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std::array<u32, 5> base_storage_bindings{};
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std::array<u32, 5> num_texture_buffers{};
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <vector>
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#include <boost/container/small_vector.hpp>
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@ -27,6 +28,9 @@ ComputePipeline::ComputePipeline(const Device& device_, DescriptorPool& descript
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vk::ShaderModule spv_module_)
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: device{device_}, update_descriptor_queue{update_descriptor_queue_}, info{info_},
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spv_module(std::move(spv_module_)) {
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std::copy_n(info.constant_buffer_used_sizes.begin(), uniform_buffer_sizes.size(),
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uniform_buffer_sizes.begin());
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auto func{[this, &descriptor_pool] {
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DescriptorLayoutBuilder builder{device.GetLogical()};
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builder.Add(info, VK_SHADER_STAGE_COMPUTE_BIT);
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@ -75,7 +79,7 @@ void ComputePipeline::Configure(Tegra::Engines::KeplerCompute& kepler_compute,
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BufferCache& buffer_cache, TextureCache& texture_cache) {
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update_descriptor_queue.Acquire();
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buffer_cache.SetEnabledComputeUniformBuffers(info.constant_buffer_mask);
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buffer_cache.SetComputeUniformBufferState(info.constant_buffer_mask, &uniform_buffer_sizes);
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buffer_cache.UnbindComputeStorageBuffers();
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size_t ssbo_index{};
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for (const auto& desc : info.storage_buffers_descriptors) {
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@ -44,6 +44,8 @@ private:
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VKUpdateDescriptorQueue& update_descriptor_queue;
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Shader::Info info;
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VideoCommon::ComputeUniformBufferSizes uniform_buffer_sizes{};
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vk::ShaderModule spv_module;
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vk::DescriptorSetLayout descriptor_set_layout;
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DescriptorAllocator descriptor_allocator;
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@ -218,10 +218,14 @@ GraphicsPipeline::GraphicsPipeline(Tegra::Engines::Maxwell3D& maxwell3d_,
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update_descriptor_queue{update_descriptor_queue_}, spv_modules{std::move(stages)} {
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std::ranges::transform(infos, stage_infos.begin(),
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[](const Shader::Info* info) { return info ? *info : Shader::Info{}; });
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std::ranges::transform(infos, enabled_uniform_buffers.begin(), [](const Shader::Info* info) {
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return info ? info->constant_buffer_mask : 0;
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});
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for (size_t stage = 0; stage < NUM_STAGES; ++stage) {
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const Shader::Info* const info{infos[stage]};
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if (!info) {
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continue;
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}
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enabled_uniform_buffer_masks[stage] = info->constant_buffer_mask;
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std::ranges::copy(info->constant_buffer_used_sizes, uniform_buffer_sizes[stage].begin());
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}
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auto func{[this, &render_pass_cache, &descriptor_pool] {
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DescriptorLayoutBuilder builder{MakeBuilder(device, stage_infos)};
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descriptor_set_layout = builder.CreateDescriptorSetLayout();
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@ -262,7 +266,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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texture_cache.SynchronizeGraphicsDescriptors();
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buffer_cache.SetEnabledUniformBuffers(enabled_uniform_buffers);
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buffer_cache.SetUniformBuffersState(enabled_uniform_buffer_masks, &uniform_buffer_sizes);
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const auto& regs{maxwell3d.regs};
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex};
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@ -130,7 +130,8 @@ private:
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std::array<vk::ShaderModule, NUM_STAGES> spv_modules;
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std::array<Shader::Info, NUM_STAGES> stage_infos;
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std::array<u32, 5> enabled_uniform_buffers{};
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std::array<u32, 5> enabled_uniform_buffer_masks{};
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VideoCommon::UniformBufferSizes uniform_buffer_sizes{};
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vk::DescriptorSetLayout descriptor_set_layout;
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DescriptorAllocator descriptor_allocator;
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