shader: add support for const buffer indirect addressing
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cd07a43724
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52895fab67
@ -124,25 +124,56 @@ std::optional<OutAttr> OutputAttrPointer(EmitContext& ctx, IR::Attribute attr) {
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Id GetCbuf(EmitContext& ctx, Id result_type, Id UniformDefinitions::*member_ptr, u32 element_size,
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Id GetCbuf(EmitContext& ctx, Id result_type, Id UniformDefinitions::*member_ptr, u32 element_size,
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const IR::Value& binding, const IR::Value& offset) {
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const IR::Value& binding, const IR::Value& offset) {
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if (!binding.IsImmediate()) {
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std::array<Id, 2> indexes;
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throw NotImplementedException("Constant buffer indexing");
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}
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const Id cbuf{ctx.cbufs[binding.U32()].*member_ptr};
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const Id uniform_type{ctx.uniform_types.*member_ptr};
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const Id uniform_type{ctx.uniform_types.*member_ptr};
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if (!offset.IsImmediate()) {
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if (offset.IsImmediate()) {
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// Hardware been proved to read the aligned offset (e.g. LDC.U32 at 6 will read offset 4)
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const Id imm_offset{ctx.Const(offset.U32() / element_size)};
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indexes = {ctx.u32_zero_value, imm_offset};
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} else {
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Id index{ctx.Def(offset)};
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Id index{ctx.Def(offset)};
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if (element_size > 1) {
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if (element_size > 1) {
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const u32 log2_element_size{static_cast<u32>(std::countr_zero(element_size))};
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const u32 log2_element_size{static_cast<u32>(std::countr_zero(element_size))};
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const Id shift{ctx.Const(log2_element_size)};
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const Id shift{ctx.Const(log2_element_size)};
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index = ctx.OpShiftRightArithmetic(ctx.U32[1], ctx.Def(offset), shift);
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index = ctx.OpShiftRightArithmetic(ctx.U32[1], ctx.Def(offset), shift);
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}
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}
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const Id access_chain{ctx.OpAccessChain(uniform_type, cbuf, ctx.u32_zero_value, index)};
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indexes = {ctx.u32_zero_value, index};
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return ctx.OpLoad(result_type, access_chain);
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}
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if (binding.IsImmediate()) {
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const Id cbuf{ctx.cbufs[binding.U32()].*member_ptr};
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const Id access_chain{ctx.OpAccessChain(uniform_type, cbuf, indexes)};
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return ctx.OpLoad(result_type, access_chain);
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} else {
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const Id index{ctx.Def(binding)};
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const Id ptr{ctx.TypePointer(spv::StorageClass::Function, result_type)};
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const Id value{ctx.AddLocalVariable(ptr, spv::StorageClass::Function)};
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const Id merge_label = ctx.OpLabel();
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std::array<Id, Info::MAX_CBUFS> buf_labels;
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std::array<Sirit::Literal, Info::MAX_CBUFS> buf_literals;
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for (u32 i = 0; i < Info::MAX_CBUFS; i++) {
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buf_labels[i] = ctx.OpLabel();
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buf_literals[i] = Sirit::Literal{i};
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}
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ctx.OpSelectionMerge(merge_label, spv::SelectionControlMask::MaskNone);
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ctx.OpSwitch(index, buf_labels[0], buf_literals, buf_labels);
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for (u32 i = 0; i < Info::MAX_CBUFS; i++) {
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ctx.AddLabel(buf_labels[i]);
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const Id cbuf{ctx.cbufs[i].*member_ptr};
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const Id access_chain{ctx.OpAccessChain(uniform_type, cbuf, indexes)};
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const Id result = ctx.OpLoad(result_type, access_chain);
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ctx.OpStore(value, result);
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ctx.OpBranch(merge_label);
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}
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ctx.AddLabel(merge_label);
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return ctx.OpLoad(result_type, value);
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}
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}
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// Hardware been proved to read the aligned offset (e.g. LDC.U32 at 6 will read offset 4)
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const Id imm_offset{ctx.Const(offset.U32() / element_size)};
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const Id access_chain{ctx.OpAccessChain(uniform_type, cbuf, ctx.u32_zero_value, imm_offset)};
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return ctx.OpLoad(result_type, access_chain);
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}
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}
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Id GetCbufU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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Id GetCbufU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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@ -29,6 +29,20 @@ void AddConstantBufferDescriptor(Info& info, u32 index, u32 count) {
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});
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});
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}
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}
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void AddRegisterIndexedLdc(Info& info) {
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// The shader can use any possible constant buffer
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info.constant_buffer_mask = (1 << Info::MAX_CBUFS) - 1;
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auto& cbufs{info.constant_buffer_descriptors};
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cbufs.clear();
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for (u32 i = 0; i < Info::MAX_CBUFS; i++) {
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cbufs.push_back(ConstantBufferDescriptor{.index = i, .count = 1});
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// The shader can use any possible access size
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info.constant_buffer_used_sizes[i] = 0x10'000;
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}
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}
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void GetPatch(Info& info, IR::Patch patch) {
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void GetPatch(Info& info, IR::Patch patch) {
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if (!IR::IsGeneric(patch)) {
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if (!IR::IsGeneric(patch)) {
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throw NotImplementedException("Reading non-generic patch {}", patch);
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throw NotImplementedException("Reading non-generic patch {}", patch);
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@ -463,10 +477,12 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::GetCbufU32x2: {
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case IR::Opcode::GetCbufU32x2: {
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const IR::Value index{inst.Arg(0)};
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const IR::Value index{inst.Arg(0)};
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const IR::Value offset{inst.Arg(1)};
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const IR::Value offset{inst.Arg(1)};
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if (!index.IsImmediate()) {
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if (index.IsImmediate()) {
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throw NotImplementedException("Constant buffer with non-immediate index");
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AddConstantBufferDescriptor(info, index.U32(), 1);
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} else {
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AddRegisterIndexedLdc(info);
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}
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}
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AddConstantBufferDescriptor(info, index.U32(), 1);
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u32 element_size{};
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u32 element_size{};
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switch (inst.GetOpcode()) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::GetCbufU8:
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case IR::Opcode::GetCbufU8:
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@ -494,11 +510,14 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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default:
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default:
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break;
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break;
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}
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}
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u32& size{info.constant_buffer_used_sizes[index.U32()]};
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if (offset.IsImmediate()) {
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if (index.IsImmediate()) {
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size = Common::AlignUp(std::max(size, offset.U32() + element_size), 16u);
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u32& size{info.constant_buffer_used_sizes[index.U32()]};
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} else {
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if (offset.IsImmediate()) {
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size = 0x10'000;
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size = Common::AlignUp(std::max(size, offset.U32() + element_size), 16u);
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} else {
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size = 0x10'000;
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}
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}
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}
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break;
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break;
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}
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}
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