shader: Implement MEMBAR
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ecb30c9072
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655f7a570a
@ -3,6 +3,7 @@ add_library(shader_recompiler STATIC
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backend/spirv/emit_context.h
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backend/spirv/emit_context.h
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backend/spirv/emit_spirv.cpp
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backend/spirv/emit_spirv.cpp
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backend/spirv/emit_spirv.h
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backend/spirv/emit_spirv.h
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backend/spirv/emit_spirv_barriers.cpp
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backend/spirv/emit_spirv_bitwise_conversion.cpp
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backend/spirv/emit_spirv_bitwise_conversion.cpp
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backend/spirv/emit_spirv_composite.cpp
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backend/spirv/emit_spirv_composite.cpp
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backend/spirv/emit_spirv_context_get_set.cpp
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backend/spirv/emit_spirv_context_get_set.cpp
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@ -63,6 +64,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/program.h
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frontend/maxwell/program.h
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frontend/maxwell/structured_control_flow.cpp
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frontend/maxwell/structured_control_flow.cpp
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frontend/maxwell/structured_control_flow.h
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frontend/maxwell/structured_control_flow.h
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frontend/maxwell/translate/impl/barrier_operations.cpp
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frontend/maxwell/translate/impl/bitfield_extract.cpp
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frontend/maxwell/translate/impl/bitfield_extract.cpp
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frontend/maxwell/translate/impl/bitfield_insert.cpp
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frontend/maxwell/translate/impl/bitfield_insert.cpp
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frontend/maxwell/translate/impl/branch_indirect.cpp
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frontend/maxwell/translate/impl/branch_indirect.cpp
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@ -28,6 +28,7 @@ void EmitSelectionMerge(EmitContext& ctx, Id merge_label);
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void EmitReturn(EmitContext& ctx);
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void EmitReturn(EmitContext& ctx);
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void EmitUnreachable(EmitContext& ctx);
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void EmitUnreachable(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx, Id continue_label);
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void EmitDemoteToHelperInvocation(EmitContext& ctx, Id continue_label);
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void EmitMemoryBarrier(EmitContext& ctx, IR::Inst* inst);
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void EmitPrologue(EmitContext& ctx);
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void EmitPrologue(EmitContext& ctx);
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void EmitEpilogue(EmitContext& ctx);
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void EmitEpilogue(EmitContext& ctx);
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void EmitGetRegister(EmitContext& ctx);
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void EmitGetRegister(EmitContext& ctx);
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40
src/shader_recompiler/backend/spirv/emit_spirv_barriers.cpp
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src/shader_recompiler/backend/spirv/emit_spirv_barriers.cpp
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@ -0,0 +1,40 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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spv::Scope MemoryScopeToSpirVScope(IR::MemoryScope scope) {
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switch (scope) {
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case IR::MemoryScope::Warp:
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return spv::Scope::Subgroup;
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case IR::MemoryScope::Workgroup:
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return spv::Scope::Workgroup;
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case IR::MemoryScope::Device:
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return spv::Scope::Device;
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case IR::MemoryScope::System:
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return spv::Scope::CrossDevice;
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case IR::MemoryScope::DontCare:
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return spv::Scope::Invocation;
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default:
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throw NotImplementedException("Unknown memory scope!");
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}
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}
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} // namespace
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void EmitMemoryBarrier(EmitContext& ctx, IR::Inst* inst) {
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const auto info{inst->Flags<IR::BarrierInstInfo>()};
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const auto semantics =
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spv::MemorySemanticsMask::AcquireRelease | spv::MemorySemanticsMask::UniformMemory |
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spv::MemorySemanticsMask::WorkgroupMemory | spv::MemorySemanticsMask::AtomicCounterMemory |
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spv::MemorySemanticsMask::ImageMemory;
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const auto scope = MemoryScopeToSpirVScope(info.scope);
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ctx.OpMemoryBarrier(ctx.Constant(ctx.U32[1], static_cast<u32>(scope)),
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ctx.Constant(ctx.U32[1], static_cast<u32>(semantics)));
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}
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} // namespace Shader::Backend::SPIRV
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@ -82,6 +82,10 @@ void IREmitter::SelectionMerge(Block* merge_block) {
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Inst(Opcode::SelectionMerge, merge_block);
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Inst(Opcode::SelectionMerge, merge_block);
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}
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}
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void IREmitter::MemoryBarrier(BarrierInstInfo info) {
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Inst(Opcode::MemoryBarrier, Flags{info});
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}
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void IREmitter::Return() {
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void IREmitter::Return() {
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block->SetReturn();
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block->SetReturn();
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Inst(Opcode::Return);
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Inst(Opcode::Return);
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@ -136,6 +136,8 @@ public:
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[[nodiscard]] Value Select(const U1& condition, const Value& true_value,
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[[nodiscard]] Value Select(const U1& condition, const Value& true_value,
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const Value& false_value);
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const Value& false_value);
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[[nodiscard]] void MemoryBarrier(BarrierInstInfo info);
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template <typename Dest, typename Source>
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template <typename Dest, typename Source>
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[[nodiscard]] Dest BitCast(const Source& value);
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[[nodiscard]] Dest BitCast(const Source& value);
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@ -25,6 +25,14 @@ enum class FpRounding : u8 {
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RZ, // Round towards zero
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RZ, // Round towards zero
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};
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};
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enum class MemoryScope : u32 {
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DontCare,
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Warp,
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Workgroup,
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Device,
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System
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};
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struct FpControl {
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struct FpControl {
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bool no_contraction{false};
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bool no_contraction{false};
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FpRounding rounding{FpRounding::DontCare};
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FpRounding rounding{FpRounding::DontCare};
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@ -32,6 +40,11 @@ struct FpControl {
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};
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};
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static_assert(sizeof(FpControl) <= sizeof(u32));
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static_assert(sizeof(FpControl) <= sizeof(u32));
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union BarrierInstInfo {
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u32 raw;
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BitField<0, 3, MemoryScope> scope;
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};
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union TextureInstInfo {
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union TextureInstInfo {
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u32 raw;
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u32 raw;
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BitField<0, 8, TextureType> type;
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BitField<0, 8, TextureType> type;
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@ -16,6 +16,9 @@ OPCODE(Return, Void,
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OPCODE(Unreachable, Void, )
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OPCODE(Unreachable, Void, )
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OPCODE(DemoteToHelperInvocation, Void, Label, )
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OPCODE(DemoteToHelperInvocation, Void, Label, )
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// Barriers
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OPCODE(MemoryBarrier, Void, )
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// Special operations
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// Special operations
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OPCODE(Prologue, Void, )
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OPCODE(Prologue, Void, )
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OPCODE(Epilogue, Void, )
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OPCODE(Epilogue, Void, )
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@ -0,0 +1,56 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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#include "shader_recompiler/frontend/maxwell/opcodes.h"
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namespace Shader::Maxwell {
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namespace {
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// Seems to be in CUDA terminology.
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enum class LocalScope : u64 {
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CTG = 0,
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GL = 1,
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SYS = 2,
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VC = 3,
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};
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IR::MemoryScope LocalScopeToMemoryScope(LocalScope scope) {
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switch (scope) {
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case LocalScope::CTG:
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return IR::MemoryScope::Warp;
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case LocalScope::GL:
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return IR::MemoryScope::Device;
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case LocalScope::SYS:
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return IR::MemoryScope::System;
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case LocalScope::VC:
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return IR::MemoryScope::Workgroup; // or should be device?
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default:
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throw NotImplementedException("Unimplemented Local Scope {}", scope);
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}
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}
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} // namespace
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void TranslatorVisitor::MEMBAR(u64 inst) {
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union {
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u64 raw;
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BitField<8, 2, LocalScope> scope;
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} membar{inst};
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IR::BarrierInstInfo info{};
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info.scope.Assign(LocalScopeToMemoryScope(membar.scope));
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ir.MemoryBarrier(info);
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}
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void TranslatorVisitor::DEPBAR() {
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// DEPBAR is a no-op
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}
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void TranslatorVisitor::BAR(u64) {
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throw NotImplementedException("Instruction {} is not implemented", Opcode::BAR);
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}
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} // namespace Shader::Maxwell
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@ -37,10 +37,6 @@ void TranslatorVisitor::B2R(u64) {
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ThrowNotImplemented(Opcode::B2R);
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ThrowNotImplemented(Opcode::B2R);
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}
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}
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void TranslatorVisitor::BAR(u64) {
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ThrowNotImplemented(Opcode::BAR);
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}
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void TranslatorVisitor::BPT(u64) {
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void TranslatorVisitor::BPT(u64) {
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ThrowNotImplemented(Opcode::BPT);
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ThrowNotImplemented(Opcode::BPT);
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}
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}
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@ -73,9 +69,6 @@ void TranslatorVisitor::CS2R(u64) {
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ThrowNotImplemented(Opcode::CS2R);
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ThrowNotImplemented(Opcode::CS2R);
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}
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}
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void TranslatorVisitor::DEPBAR() {
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// DEPBAR is a no-op
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}
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void TranslatorVisitor::FCHK_reg(u64) {
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void TranslatorVisitor::FCHK_reg(u64) {
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ThrowNotImplemented(Opcode::FCHK_reg);
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ThrowNotImplemented(Opcode::FCHK_reg);
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@ -189,10 +182,6 @@ void TranslatorVisitor::LONGJMP(u64) {
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ThrowNotImplemented(Opcode::LONGJMP);
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ThrowNotImplemented(Opcode::LONGJMP);
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}
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}
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void TranslatorVisitor::MEMBAR(u64) {
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ThrowNotImplemented(Opcode::MEMBAR);
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}
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void TranslatorVisitor::NOP(u64) {
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void TranslatorVisitor::NOP(u64) {
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ThrowNotImplemented(Opcode::NOP);
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ThrowNotImplemented(Opcode::NOP);
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}
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}
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