added thumb mode emulation
This commit is contained in:
bunnei
parent
c9b5b89e21
commit
7bf24c066b
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@ -145,6 +145,7 @@
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<ClCompile Include="src\arm\armvirt.cpp" />
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<ClCompile Include="src\arm\disassembler\arm_disasm.cpp" />
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<ClCompile Include="src\arm\mmu\arm1176jzf_s_mmu.cpp" />
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<ClCompile Include="src\arm\thumbemu.cpp" />
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<ClCompile Include="src\core.cpp" />
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<ClCompile Include="src\core_timing.cpp" />
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<ClCompile Include="src\elf\elf_reader.cpp" />
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@ -40,6 +40,9 @@
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<ClCompile Include="src\arm\mmu\arm1176jzf_s_mmu.cpp">
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<Filter>arm\mmu</Filter>
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</ClCompile>
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<ClCompile Include="src\arm\thumbemu.cpp">
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<Filter>arm</Filter>
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</ClCompile>
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</ItemGroup>
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<ItemGroup>
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<Filter Include="arm">
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@ -936,10 +936,10 @@ ARMul_Emulate26 (ARMul_State * state)
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pipelined PC value is used when executing Thumb code, and also for
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dealing with the BL instruction. */
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if (TFLAG) {
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ARMword new;
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ARMword new_instr;
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/* Check if in Thumb mode. */
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switch (ARMul_ThumbDecode (state, pc, instr, &new)) {
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switch (ARMul_ThumbDecode(state, pc, instr, &new_instr)) {
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case t_undefined:
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/* This is a Thumb instruction. */
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ARMul_UndefInstr (state, instr);
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@ -952,7 +952,7 @@ ARMul_Emulate26 (ARMul_State * state)
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case t_decoded:
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/* ARM instruction available. */
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//printf("t decode %04lx -> %08lx\n", instr & 0xffff, new);
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instr = new;
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instr = new_instr;
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/* So continue instruction decoding. */
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break;
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default:
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@ -4,6 +4,7 @@
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#include "common.h"
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#define MODE32
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#define MODET
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typedef struct
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{
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@ -0,0 +1,513 @@
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/* thumbemu.c -- Thumb instruction emulation.
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Copyright (C) 1996, Cygnus Software Technologies Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* We can provide simple Thumb simulation by decoding the Thumb
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instruction into its corresponding ARM instruction, and using the
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existing ARM simulator. */
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#include "skyeye_defs.h"
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#ifndef MODET /* required for the Thumb instruction support */
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#if 1
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#error "MODET needs to be defined for the Thumb world to work"
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#else
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#define MODET (1)
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#endif
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#endif
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#include "armdefs.h"
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#include "armemu.h"
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#include "armos.h"
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/* Decode a 16bit Thumb instruction. The instruction is in the low
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16-bits of the tinstr field, with the following Thumb instruction
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held in the high 16-bits. Passing in two Thumb instructions allows
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easier simulation of the special dual BL instruction. */
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tdstate
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ARMul_ThumbDecode (
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ARMul_State *state,
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ARMword pc,
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ARMword tinstr,
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ARMword *ainstr)
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{
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tdstate valid = t_decoded; /* default assumes a valid instruction */
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ARMword next_instr;
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if (state->bigendSig) {
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next_instr = tinstr & 0xFFFF;
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tinstr >>= 16;
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}
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else {
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next_instr = tinstr >> 16;
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tinstr &= 0xFFFF;
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}
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#if 1 /* debugging to catch non updates */
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*ainstr = 0xDEADC0DE;
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#endif
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switch ((tinstr & 0xF800) >> 11) {
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case 0: /* LSL */
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case 1: /* LSR */
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case 2: /* ASR */
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/* Format 1 */
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*ainstr = 0xE1B00000 /* base opcode */
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| ((tinstr & 0x1800) >> (11 - 5)) /* shift type */
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|((tinstr & 0x07C0) << (7 - 6)) /* imm5 */
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|((tinstr & 0x0038) >> 3) /* Rs */
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|((tinstr & 0x0007) << 12); /* Rd */
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break;
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case 3: /* ADD/SUB */
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/* Format 2 */
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{
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ARMword subset[4] = {
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0xE0900000, /* ADDS Rd,Rs,Rn */
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0xE0500000, /* SUBS Rd,Rs,Rn */
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0xE2900000, /* ADDS Rd,Rs,#imm3 */
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0xE2500000 /* SUBS Rd,Rs,#imm3 */
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};
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/* It is quicker indexing into a table, than performing switch
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or conditionals: */
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*ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */
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|((tinstr & 0x01C0) >> 6) /* Rn or imm3 */
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|((tinstr & 0x0038) << (16 - 3)) /* Rs */
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|((tinstr & 0x0007) << (12 - 0)); /* Rd */
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}
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break;
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case 4: /* MOV */
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case 5: /* CMP */
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case 6: /* ADD */
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case 7: /* SUB */
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/* Format 3 */
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{
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ARMword subset[4] = {
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0xE3B00000, /* MOVS Rd,#imm8 */
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0xE3500000, /* CMP Rd,#imm8 */
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0xE2900000, /* ADDS Rd,Rd,#imm8 */
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0xE2500000, /* SUBS Rd,Rd,#imm8 */
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};
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*ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */
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|((tinstr & 0x00FF) >> 0) /* imm8 */
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|((tinstr & 0x0700) << (16 - 8)) /* Rn */
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|((tinstr & 0x0700) << (12 - 8)); /* Rd */
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}
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break;
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case 8: /* Arithmetic and high register transfers */
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/* TODO: Since the subsets for both Format 4 and Format 5
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instructions are made up of different ARM encodings, we could
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save the following conditional, and just have one large
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subset. */
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if ((tinstr & (1 << 10)) == 0) {
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/* Format 4 */
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enum OpcodeType { t_norm, t_shift, t_neg, t_mul };
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struct ThumbOpcode {
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ARMword opcode;
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OpcodeType otype;
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};
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ThumbOpcode subset[16] = {
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{
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0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
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{
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0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
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{
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0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
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{
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0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
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{
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0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */
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{
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0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */
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{
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0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */
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{
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0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
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{
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0xE1100000, t_norm}, /* TST Rd,Rs */
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{
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0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */
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{
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0xE1500000, t_norm}, /* CMP Rd,Rs */
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{
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0xE1700000, t_norm}, /* CMN Rd,Rs */
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{
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0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */
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{
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0xE0100090, t_mul}, /* MULS Rd,Rd,Rs */
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{
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0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */
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{
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0xE1F00000, t_norm} /* MVNS Rd,Rs */
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};
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*ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */
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switch (subset[(tinstr & 0x03C0) >> 6].otype) {
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case t_norm:
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*ainstr |= ((tinstr & 0x0007) << 16) /* Rn */
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|((tinstr & 0x0007) << 12) /* Rd */
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|((tinstr & 0x0038) >> 3); /* Rs */
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break;
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case t_shift:
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*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
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|((tinstr & 0x0007) >> 0) /* Rm */
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|((tinstr & 0x0038) << (8 - 3)); /* Rs */
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break;
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case t_neg:
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*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
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|((tinstr & 0x0038) << (16 - 3)); /* Rn */
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break;
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case t_mul:
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*ainstr |= ((tinstr & 0x0007) << 16) /* Rd */
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|((tinstr & 0x0007) << 8) /* Rs */
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|((tinstr & 0x0038) >> 3); /* Rm */
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break;
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}
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}
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else {
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/* Format 5 */
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ARMword Rd = ((tinstr & 0x0007) >> 0);
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ARMword Rs = ((tinstr & 0x0038) >> 3);
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if (tinstr & (1 << 7))
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Rd += 8;
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if (tinstr & (1 << 6))
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Rs += 8;
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switch ((tinstr & 0x03C0) >> 6) {
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case 0x1: /* ADD Rd,Rd,Hs */
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case 0x2: /* ADD Hd,Hd,Rs */
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case 0x3: /* ADD Hd,Hd,Hs */
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*ainstr = 0xE0800000 /* base */
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| (Rd << 16) /* Rn */
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|(Rd << 12) /* Rd */
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|(Rs << 0); /* Rm */
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break;
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case 0x5: /* CMP Rd,Hs */
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case 0x6: /* CMP Hd,Rs */
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case 0x7: /* CMP Hd,Hs */
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*ainstr = 0xE1500000 /* base */
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| (Rd << 16) /* Rn */
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|(Rd << 12) /* Rd */
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|(Rs << 0); /* Rm */
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break;
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case 0x9: /* MOV Rd,Hs */
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case 0xA: /* MOV Hd,Rs */
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case 0xB: /* MOV Hd,Hs */
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*ainstr = 0xE1A00000 /* base */
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| (Rd << 16) /* Rn */
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|(Rd << 12) /* Rd */
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|(Rs << 0); /* Rm */
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break;
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case 0xC: /* BX Rs */
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case 0xD: /* BX Hs */
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*ainstr = 0xE12FFF10 /* base */
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| ((tinstr & 0x0078) >> 3); /* Rd */
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break;
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case 0x0: /* UNDEFINED */
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case 0x4: /* UNDEFINED */
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case 0x8: /* UNDEFINED */
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valid = t_undefined;
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break;
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case 0xE: /* BLX */
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case 0xF: /* BLX */
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if (state->is_v5) {
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*ainstr = 0xE1200030 /* base */
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|(Rs << 0); /* Rm */
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} else {
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valid = t_undefined;
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}
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break;
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}
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}
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break;
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case 9: /* LDR Rd,[PC,#imm8] */
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/* Format 6 */
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*ainstr = 0xE59F0000 /* base */
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| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
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|((tinstr & 0x00FF) << (2 - 0)); /* off8 */
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break;
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case 10:
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case 11:
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/* TODO: Format 7 and Format 8 perform the same ARM encoding, so
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the following could be merged into a single subset, saving on
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the following boolean: */
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if ((tinstr & (1 << 9)) == 0) {
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/* Format 7 */
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ARMword subset[4] = {
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0xE7800000, /* STR Rd,[Rb,Ro] */
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0xE7C00000, /* STRB Rd,[Rb,Ro] */
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0xE7900000, /* LDR Rd,[Rb,Ro] */
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0xE7D00000 /* LDRB Rd,[Rb,Ro] */
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};
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*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
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|((tinstr & 0x0007) << (12 - 0)) /* Rd */
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|((tinstr & 0x0038) << (16 - 3)) /* Rb */
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|((tinstr & 0x01C0) >> 6); /* Ro */
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}
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else {
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/* Format 8 */
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ARMword subset[4] = {
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0xE18000B0, /* STRH Rd,[Rb,Ro] */
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0xE19000D0, /* LDRSB Rd,[Rb,Ro] */
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0xE19000B0, /* LDRH Rd,[Rb,Ro] */
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0xE19000F0 /* LDRSH Rd,[Rb,Ro] */
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};
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*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
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|((tinstr & 0x0007) << (12 - 0)) /* Rd */
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|((tinstr & 0x0038) << (16 - 3)) /* Rb */
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|((tinstr & 0x01C0) >> 6); /* Ro */
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}
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break;
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case 12: /* STR Rd,[Rb,#imm5] */
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case 13: /* LDR Rd,[Rb,#imm5] */
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case 14: /* STRB Rd,[Rb,#imm5] */
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case 15: /* LDRB Rd,[Rb,#imm5] */
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/* Format 9 */
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{
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ARMword subset[4] = {
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0xE5800000, /* STR Rd,[Rb,#imm5] */
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0xE5900000, /* LDR Rd,[Rb,#imm5] */
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0xE5C00000, /* STRB Rd,[Rb,#imm5] */
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0xE5D00000 /* LDRB Rd,[Rb,#imm5] */
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};
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/* The offset range defends on whether we are transferring a
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byte or word value: */
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*ainstr = subset[(tinstr & 0x1800) >> 11] /* base */
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|((tinstr & 0x0007) << (12 - 0)) /* Rd */
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|((tinstr & 0x0038) << (16 - 3)) /* Rb */
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|((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */
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}
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break;
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case 16: /* STRH Rd,[Rb,#imm5] */
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case 17: /* LDRH Rd,[Rb,#imm5] */
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/* Format 10 */
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*ainstr = ((tinstr & (1 << 11)) /* base */
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? 0xE1D000B0 /* LDRH */
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: 0xE1C000B0) /* STRH */
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|((tinstr & 0x0007) << (12 - 0)) /* Rd */
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|((tinstr & 0x0038) << (16 - 3)) /* Rb */
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|((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */
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|((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */
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break;
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case 18: /* STR Rd,[SP,#imm8] */
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case 19: /* LDR Rd,[SP,#imm8] */
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/* Format 11 */
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*ainstr = ((tinstr & (1 << 11)) /* base */
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? 0xE59D0000 /* LDR */
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: 0xE58D0000) /* STR */
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|((tinstr & 0x0700) << (12 - 8)) /* Rd */
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|((tinstr & 0x00FF) << 2); /* off8 */
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break;
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case 20: /* ADD Rd,PC,#imm8 */
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case 21: /* ADD Rd,SP,#imm8 */
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/* Format 12 */
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if ((tinstr & (1 << 11)) == 0) {
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/* NOTE: The PC value used here should by word aligned */
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/* We encode shift-left-by-2 in the rotate immediate field,
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so no shift of off8 is needed. */
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*ainstr = 0xE28F0F00 /* base */
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| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
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|(tinstr & 0x00FF); /* off8 */
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}
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else {
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/* We encode shift-left-by-2 in the rotate immediate field,
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so no shift of off8 is needed. */
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*ainstr = 0xE28D0F00 /* base */
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| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
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|(tinstr & 0x00FF); /* off8 */
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}
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break;
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case 22:
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case 23:
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if ((tinstr & 0x0F00) == 0x0000) {
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/* Format 13 */
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/* NOTE: The instruction contains a shift left of 2
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equivalent (implemented as ROR #30): */
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*ainstr = ((tinstr & (1 << 7)) /* base */
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? 0xE24DDF00 /* SUB */
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: 0xE28DDF00) /* ADD */
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|(tinstr & 0x007F); /* off7 */
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}
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else if ((tinstr & 0x0F00) == 0x0e00)
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*ainstr = 0xEF000000 | SWI_Breakpoint;
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else {
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/* Format 14 */
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ARMword subset[4] = {
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0xE92D0000, /* STMDB sp!,{rlist} */
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0xE92D4000, /* STMDB sp!,{rlist,lr} */
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0xE8BD0000, /* LDMIA sp!,{rlist} */
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0xE8BD8000 /* LDMIA sp!,{rlist,pc} */
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};
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*ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */
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|(tinstr & 0x00FF); /* mask8 */
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}
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break;
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case 24: /* STMIA */
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case 25: /* LDMIA */
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/* Format 15 */
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*ainstr = ((tinstr & (1 << 11)) /* base */
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? 0xE8B00000 /* LDMIA */
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: 0xE8A00000) /* STMIA */
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|((tinstr & 0x0700) << (16 - 8)) /* Rb */
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|(tinstr & 0x00FF); /* mask8 */
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break;
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case 26: /* Bcc */
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case 27: /* Bcc/SWI */
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if ((tinstr & 0x0F00) == 0x0F00) {
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if (tinstr == (ARMul_ABORTWORD & 0xffff) &&
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state->AbortAddr == pc) {
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*ainstr = ARMul_ABORTWORD;
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break;
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}
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/* Format 17 : SWI */
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*ainstr = 0xEF000000;
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/* Breakpoint must be handled specially. */
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if ((tinstr & 0x00FF) == 0x18)
|
||||
*ainstr |= ((tinstr & 0x00FF) << 16);
|
||||
/* New breakpoint value. See gdb/arm-tdep.c */
|
||||
else if ((tinstr & 0x00FF) == 0xFE)
|
||||
*ainstr |= SWI_Breakpoint;
|
||||
else
|
||||
*ainstr |= (tinstr & 0x00FF);
|
||||
}
|
||||
else if ((tinstr & 0x0F00) != 0x0E00) {
|
||||
/* Format 16 */
|
||||
int doit = FALSE;
|
||||
/* TODO: Since we are doing a switch here, we could just add
|
||||
the SWI and undefined instruction checks into this
|
||||
switch to same on a couple of conditionals: */
|
||||
switch ((tinstr & 0x0F00) >> 8) {
|
||||
case EQ:
|
||||
doit = ZFLAG;
|
||||
break;
|
||||
case NE:
|
||||
doit = !ZFLAG;
|
||||
break;
|
||||
case VS:
|
||||
doit = VFLAG;
|
||||
break;
|
||||
case VC:
|
||||
doit = !VFLAG;
|
||||
break;
|
||||
case MI:
|
||||
doit = NFLAG;
|
||||
break;
|
||||
case PL:
|
||||
doit = !NFLAG;
|
||||
break;
|
||||
case CS:
|
||||
doit = CFLAG;
|
||||
break;
|
||||
case CC:
|
||||
doit = !CFLAG;
|
||||
break;
|
||||
case HI:
|
||||
doit = (CFLAG && !ZFLAG);
|
||||
break;
|
||||
case LS:
|
||||
doit = (!CFLAG || ZFLAG);
|
||||
break;
|
||||
case GE:
|
||||
doit = ((!NFLAG && !VFLAG)
|
||||
|| (NFLAG && VFLAG));
|
||||
break;
|
||||
case LT:
|
||||
doit = ((NFLAG && !VFLAG)
|
||||
|| (!NFLAG && VFLAG));
|
||||
break;
|
||||
case GT:
|
||||
doit = ((!NFLAG && !VFLAG && !ZFLAG)
|
||||
|| (NFLAG && VFLAG && !ZFLAG));
|
||||
break;
|
||||
case LE:
|
||||
doit = ((NFLAG && !VFLAG)
|
||||
|| (!NFLAG && VFLAG)) || ZFLAG;
|
||||
break;
|
||||
}
|
||||
if (doit) {
|
||||
state->Reg[15] = (pc + 4
|
||||
+ (((tinstr & 0x7F) << 1)
|
||||
| ((tinstr & (1 << 7)) ?
|
||||
0xFFFFFF00 : 0)));
|
||||
FLUSHPIPE;
|
||||
}
|
||||
valid = t_branch;
|
||||
}
|
||||
else /* UNDEFINED : cc=1110(AL) uses different format */
|
||||
valid = t_undefined;
|
||||
break;
|
||||
case 28: /* B */
|
||||
/* Format 18 */
|
||||
state->Reg[15] = (pc + 4 + (((tinstr & 0x3FF) << 1)
|
||||
| ((tinstr & (1 << 10)) ?
|
||||
0xFFFFF800 : 0)));
|
||||
FLUSHPIPE;
|
||||
valid = t_branch;
|
||||
break;
|
||||
case 29:
|
||||
if(tinstr & 0x1)
|
||||
valid = t_undefined;
|
||||
else{
|
||||
/* BLX 1 for armv5t and above */
|
||||
ARMword tmp = (pc + 2);
|
||||
state->Reg[15] =
|
||||
(state->Reg[14] + ((tinstr & 0x07FF) << 1)) & 0xFFFFFFFC;
|
||||
state->Reg[14] = (tmp | 1);
|
||||
CLEART;
|
||||
DEBUG_LOG(ARM11, "In %s, After BLX(1),LR=0x%x,PC=0x%x, offset=0x%x\n", __FUNCTION__, state->Reg[14], state->Reg[15], (tinstr &0x7FF) << 1);
|
||||
valid = t_branch;
|
||||
FLUSHPIPE;
|
||||
}
|
||||
break;
|
||||
case 30: /* BL instruction 1 */
|
||||
/* Format 19 */
|
||||
/* There is no single ARM instruction equivalent for this Thumb
|
||||
instruction. To keep the simulation simple (from the user
|
||||
perspective) we check if the following instruction is the
|
||||
second half of this BL, and if it is we simulate it
|
||||
immediately. */
|
||||
state->Reg[14] = state->Reg[15]
|
||||
+ (((tinstr & 0x07FF) << 12)
|
||||
| ((tinstr & (1 << 10)) ? 0xFF800000 : 0));
|
||||
valid = t_branch; /* in-case we don't have the 2nd half */
|
||||
//tinstr = next_instr; /* move the instruction down */
|
||||
//if (((tinstr & 0xF800) >> 11) != 31)
|
||||
// break; /* exit, since not correct instruction */
|
||||
/* else we fall through to process the second half of the BL */
|
||||
//pc += 2; /* point the pc at the 2nd half */
|
||||
state->Reg[15] = pc + 2;
|
||||
FLUSHPIPE;
|
||||
break;
|
||||
case 31: /* BL instruction 2 */
|
||||
/* Format 19 */
|
||||
/* There is no single ARM instruction equivalent for this
|
||||
instruction. Also, it should only ever be matched with the
|
||||
fmt19 "BL instruction 1" instruction. However, we do allow
|
||||
the simulation of it on its own, with undefined results if
|
||||
r14 is not suitably initialised. */
|
||||
{
|
||||
ARMword tmp = (pc + 2);
|
||||
state->Reg[15] =
|
||||
(state->Reg[14] + ((tinstr & 0x07FF) << 1));
|
||||
state->Reg[14] = (tmp | 1);
|
||||
valid = t_branch;
|
||||
FLUSHPIPE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
Loading…
Reference in New Issue