shader: Implement S2R Tid{XYZ} and CtaId{XYZ}
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@ -1513,6 +1513,16 @@ private:
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return "uintBitsToFloat(config_pack[2])";
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}
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template <u32 element>
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std::string LocalInvocationId(Operation) {
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return "utof(gl_LocalInvocationID"s + GetSwizzle(element) + ')';
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}
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template <u32 element>
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std::string WorkGroupId(Operation) {
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return "utof(gl_WorkGroupID"s + GetSwizzle(element) + ')';
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}
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static constexpr OperationDecompilersArray operation_decompilers = {
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&GLSLDecompiler::Assign,
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@ -1652,6 +1662,12 @@ private:
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&GLSLDecompiler::EndPrimitive,
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&GLSLDecompiler::YNegate,
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&GLSLDecompiler::LocalInvocationId<0>,
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&GLSLDecompiler::LocalInvocationId<1>,
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&GLSLDecompiler::LocalInvocationId<2>,
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&GLSLDecompiler::WorkGroupId<0>,
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&GLSLDecompiler::WorkGroupId<1>,
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&GLSLDecompiler::WorkGroupId<2>,
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};
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std::string GetRegister(u32 index) const {
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@ -1035,6 +1035,18 @@ private:
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return {};
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}
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template <u32 element>
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Id LocalInvocationId(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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template <u32 element>
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Id WorkGroupId(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id DeclareBuiltIn(spv::BuiltIn builtin, spv::StorageClass storage, Id type,
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const std::string& name) {
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const Id id = OpVariable(type, storage);
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@ -1291,6 +1303,12 @@ private:
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&SPIRVDecompiler::EndPrimitive,
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&SPIRVDecompiler::YNegate,
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&SPIRVDecompiler::LocalInvocationId<0>,
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&SPIRVDecompiler::LocalInvocationId<1>,
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&SPIRVDecompiler::LocalInvocationId<2>,
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&SPIRVDecompiler::WorkGroupId<0>,
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&SPIRVDecompiler::WorkGroupId<1>,
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&SPIRVDecompiler::WorkGroupId<2>,
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};
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const ShaderIR& ir;
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@ -13,6 +13,7 @@ using Tegra::Shader::ConditionCode;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::SystemVariable;
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u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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@ -58,20 +59,33 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::MOV_SYS: {
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switch (instr.sys20) {
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case Tegra::Shader::SystemVariable::InvocationInfo: {
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LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete");
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SetRegister(bb, instr.gpr0, Immediate(0u));
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break;
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}
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case Tegra::Shader::SystemVariable::Ydirection: {
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// Config pack's third value is Y_NEGATE's state.
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SetRegister(bb, instr.gpr0, Operation(OperationCode::YNegate));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled system move: {}", static_cast<u32>(instr.sys20.Value()));
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}
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const Node value = [&]() {
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switch (instr.sys20) {
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case SystemVariable::Ydirection:
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return Operation(OperationCode::YNegate);
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case SystemVariable::InvocationInfo:
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LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete");
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return Immediate(0u);
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case SystemVariable::TidX:
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return Operation(OperationCode::LocalInvocationIdX);
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case SystemVariable::TidY:
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return Operation(OperationCode::LocalInvocationIdY);
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case SystemVariable::TidZ:
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return Operation(OperationCode::LocalInvocationIdZ);
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case SystemVariable::CtaIdX:
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return Operation(OperationCode::WorkGroupIdX);
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case SystemVariable::CtaIdY:
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return Operation(OperationCode::WorkGroupIdY);
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case SystemVariable::CtaIdZ:
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return Operation(OperationCode::WorkGroupIdZ);
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default:
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UNIMPLEMENTED_MSG("Unhandled system move: {}",
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static_cast<u32>(instr.sys20.Value()));
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return Immediate(0u);
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}
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}();
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::BRA: {
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@ -181,7 +181,13 @@ enum class OperationCode {
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EmitVertex, /// () -> void
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EndPrimitive, /// () -> void
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YNegate, /// () -> float
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YNegate, /// () -> float
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LocalInvocationIdX, /// () -> uint
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LocalInvocationIdY, /// () -> uint
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LocalInvocationIdZ, /// () -> uint
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WorkGroupIdX, /// () -> uint
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WorkGroupIdY, /// () -> uint
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WorkGroupIdZ, /// () -> uint
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Amount,
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};
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