Dyncom: Remove disassembler code
Had licensing issue around it, in addition to several bugs. Closes #1632, #1280
This commit is contained in:
Yuri Kunde Schlesner
parent
f0a582b218
commit
d97b977540
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@ -1,5 +1,4 @@
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set(SRCS
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arm/disassembler/arm_disasm.cpp
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arm/dynarmic/arm_dynarmic.cpp
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arm/dynarmic/arm_dynarmic_cp15.cpp
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arm/dyncom/arm_dyncom.cpp
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@ -178,7 +177,6 @@ set(SRCS
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set(HEADERS
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arm/arm_interface.h
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arm/disassembler/arm_disasm.h
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arm/dynarmic/arm_dynarmic.h
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arm/dynarmic/arm_dynarmic_cp15.h
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arm/dyncom/arm_dyncom.h
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File diff suppressed because it is too large
Load Diff
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@ -1,238 +0,0 @@
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// Copyright 2006 The Android Open Source Project
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#pragma once
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#include <string>
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#include "common/common_types.h"
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// Note: this list of opcodes must match the list used to initialize
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// the opflags[] array in opcode.cpp.
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enum Opcode {
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OP_INVALID,
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OP_UNDEFINED,
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OP_ADC,
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OP_ADD,
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OP_AND,
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OP_B,
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OP_BL,
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OP_BIC,
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OP_BKPT,
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OP_BLX,
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OP_BX,
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OP_CDP,
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OP_CLREX,
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OP_CLZ,
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OP_CMN,
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OP_CMP,
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OP_EOR,
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OP_LDC,
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OP_LDM,
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OP_LDR,
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OP_LDRB,
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OP_LDRBT,
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OP_LDREX,
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OP_LDREXB,
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OP_LDREXD,
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OP_LDREXH,
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OP_LDRH,
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OP_LDRSB,
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OP_LDRSH,
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OP_LDRT,
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OP_MCR,
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OP_MLA,
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OP_MOV,
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OP_MRC,
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OP_MRS,
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OP_MSR,
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OP_MUL,
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OP_MVN,
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OP_NOP,
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OP_ORR,
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OP_PKH,
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OP_PLD,
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OP_QADD16,
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OP_QADD8,
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OP_QASX,
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OP_QSAX,
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OP_QSUB16,
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OP_QSUB8,
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OP_REV,
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OP_REV16,
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OP_REVSH,
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OP_RSB,
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OP_RSC,
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OP_SADD16,
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OP_SADD8,
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OP_SASX,
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OP_SBC,
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OP_SEL,
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OP_SEV,
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OP_SHADD16,
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OP_SHADD8,
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OP_SHASX,
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OP_SHSAX,
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OP_SHSUB16,
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OP_SHSUB8,
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OP_SMLAD,
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OP_SMLAL,
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OP_SMLALD,
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OP_SMLSD,
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OP_SMLSLD,
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OP_SMMLA,
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OP_SMMLS,
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OP_SMMUL,
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OP_SMUAD,
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OP_SMULL,
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OP_SMUSD,
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OP_SSAT,
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OP_SSAT16,
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OP_SSAX,
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OP_SSUB16,
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OP_SSUB8,
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OP_STC,
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OP_STM,
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OP_STR,
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OP_STRB,
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OP_STRBT,
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OP_STREX,
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OP_STREXB,
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OP_STREXD,
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OP_STREXH,
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OP_STRH,
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OP_STRT,
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OP_SUB,
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OP_SWI,
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OP_SWP,
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OP_SWPB,
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OP_SXTAB,
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OP_SXTAB16,
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OP_SXTAH,
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OP_SXTB,
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OP_SXTB16,
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OP_SXTH,
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OP_TEQ,
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OP_TST,
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OP_UADD16,
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OP_UADD8,
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OP_UASX,
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OP_UHADD16,
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OP_UHADD8,
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OP_UHASX,
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OP_UHSAX,
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OP_UHSUB16,
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OP_UHSUB8,
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OP_UMLAL,
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OP_UMULL,
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OP_UQADD16,
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OP_UQADD8,
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OP_UQASX,
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OP_UQSAX,
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OP_UQSUB16,
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OP_UQSUB8,
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OP_USAD8,
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OP_USADA8,
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OP_USAT,
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OP_USAT16,
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OP_USAX,
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OP_USUB16,
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OP_USUB8,
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OP_UXTAB,
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OP_UXTAB16,
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OP_UXTAH,
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OP_UXTB,
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OP_UXTB16,
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OP_UXTH,
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OP_WFE,
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OP_WFI,
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OP_YIELD,
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// Define thumb opcodes
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OP_THUMB_UNDEFINED,
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OP_THUMB_ADC,
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OP_THUMB_ADD,
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OP_THUMB_AND,
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OP_THUMB_ASR,
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OP_THUMB_B,
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OP_THUMB_BIC,
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OP_THUMB_BKPT,
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OP_THUMB_BL,
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OP_THUMB_BLX,
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OP_THUMB_BX,
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OP_THUMB_CMN,
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OP_THUMB_CMP,
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OP_THUMB_EOR,
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OP_THUMB_LDMIA,
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OP_THUMB_LDR,
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OP_THUMB_LDRB,
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OP_THUMB_LDRH,
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OP_THUMB_LDRSB,
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OP_THUMB_LDRSH,
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OP_THUMB_LSL,
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OP_THUMB_LSR,
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OP_THUMB_MOV,
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OP_THUMB_MUL,
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OP_THUMB_MVN,
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OP_THUMB_NEG,
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OP_THUMB_ORR,
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OP_THUMB_POP,
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OP_THUMB_PUSH,
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OP_THUMB_ROR,
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OP_THUMB_SBC,
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OP_THUMB_STMIA,
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OP_THUMB_STR,
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OP_THUMB_STRB,
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OP_THUMB_STRH,
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OP_THUMB_SUB,
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OP_THUMB_SWI,
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OP_THUMB_TST,
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OP_END // must be last
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};
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class ARM_Disasm {
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public:
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static std::string Disassemble(u32 addr, u32 insn);
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static Opcode Decode(u32 insn);
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private:
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static Opcode Decode00(u32 insn);
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static Opcode Decode01(u32 insn);
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static Opcode Decode10(u32 insn);
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static Opcode Decode11(u32 insn);
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static Opcode DecodeSyncPrimitive(u32 insn);
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static Opcode DecodeParallelAddSub(u32 insn);
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static Opcode DecodePackingSaturationReversal(u32 insn);
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static Opcode DecodeMUL(u32 insn);
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static Opcode DecodeMSRImmAndHints(u32 insn);
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static Opcode DecodeMediaMulDiv(u32 insn);
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static Opcode DecodeMedia(u32 insn);
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static Opcode DecodeLDRH(u32 insn);
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static Opcode DecodeALU(u32 insn);
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static std::string DisassembleALU(Opcode opcode, u32 insn);
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static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn);
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static std::string DisassembleBX(u32 insn);
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static std::string DisassembleBKPT(u32 insn);
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static std::string DisassembleCLZ(u32 insn);
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static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn);
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static std::string DisassembleMemblock(Opcode opcode, u32 insn);
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static std::string DisassembleMem(u32 insn);
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static std::string DisassembleMemHalf(u32 insn);
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static std::string DisassembleMCR(Opcode opcode, u32 insn);
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static std::string DisassembleMLA(Opcode opcode, u32 insn);
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static std::string DisassembleUMLAL(Opcode opcode, u32 insn);
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static std::string DisassembleMUL(Opcode opcode, u32 insn);
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static std::string DisassembleMRS(u32 insn);
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static std::string DisassembleMSR(u32 insn);
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static std::string DisassembleNoOperands(Opcode opcode, u32 insn);
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static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn);
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static std::string DisassemblePKH(u32 insn);
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static std::string DisassemblePLD(u32 insn);
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static std::string DisassembleREV(Opcode opcode, u32 insn);
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static std::string DisassembleREX(Opcode opcode, u32 insn);
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static std::string DisassembleSAT(Opcode opcode, u32 insn);
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static std::string DisassembleSEL(u32 insn);
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static std::string DisassembleSWI(u32 insn);
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static std::string DisassembleSWP(Opcode opcode, u32 insn);
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static std::string DisassembleXT(Opcode opcode, u32 insn);
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};
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@ -10,7 +10,6 @@
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "core/arm/dyncom/arm_dyncom_dec.h"
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#include "core/arm/dyncom/arm_dyncom_interpreter.h"
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#include "core/arm/dyncom/arm_dyncom_run.h"
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@ -828,10 +827,8 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
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int idx;
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if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
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LOG_ERROR(Core_ARM11,
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"Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %s [%08" PRIX32 "]",
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phys_addr, disasm.c_str(), inst);
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LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
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phys_addr, inst);
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LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
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cpu->TFlag, cpu->Reg[15]);
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CITRA_IGNORE_EXIT(-1);
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