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Merge pull request #568 from bunnei/lop 

gl_shader_decompiler: Implement LOP instructions.
This commit is contained in:
bunnei 2018-06-17 17:44:38 -04:00 committed by GitHub
parent 3c43ea5c68 afdd657d30
commit f9af74201c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 84 additions and 63 deletions
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19
src/video_core/engines/shader_bytecode.h
View File

@ -229,11 +229,19 @@ union Instruction {
BitField<42, 1, u64> negate_pred;
} fmnmx;
union {
BitField<39, 1, u64> invert_a;
BitField<40, 1, u64> invert_b;
BitField<41, 2, LogicOperation> operation;
BitField<44, 2, u64> unk44;
BitField<48, 3, Pred> pred48;
} lop;
union {
BitField<53, 2, LogicOperation> operation;
BitField<55, 1, u64> invert_a;
BitField<56, 1, u64> invert_b;
} lop;
} lop32i;
float GetImm20_19() const {
float result{};
@ -476,6 +484,9 @@ public:
I2I_C,
I2I_R,
I2I_IMM,
LOP_C,
LOP_R,
LOP_IMM,
LOP32I,
MOV_C,
MOV_R,
@ -518,7 +529,6 @@ public:
ArithmeticInteger,
ArithmeticIntegerImmediate,
Bfe,
Logic,
Shift,
Ffma,
Flow,
@ -676,7 +686,10 @@ private:
INST("0100110000000---", Id::BFE_C, Type::Bfe, "BFE_C"),
INST("0101110000000---", Id::BFE_R, Type::Bfe, "BFE_R"),
INST("0011100-00000---", Id::BFE_IMM, Type::Bfe, "BFE_IMM"),
INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
INST("0100110001000---", Id::LOP_C, Type::ArithmeticInteger, "LOP_C"),
INST("0101110001000---", Id::LOP_R, Type::ArithmeticInteger, "LOP_R"),
INST("0011100001000---", Id::LOP_IMM, Type::ArithmeticInteger, "LOP_IMM"),
INST("000001----------", Id::LOP32I, Type::ArithmeticIntegerImmediate, "LOP32I"),
INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"),
INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"),
INST("0011100-01001---", Id::SHL_IMM, Type::Shift, "SHL_IMM"),

128
src/video_core/renderer_opengl/gl_shader_decompiler.cpp
View File

@ -16,6 +16,7 @@ namespace Decompiler {
using Tegra::Shader::Attribute;
using Tegra::Shader::Instruction;
using Tegra::Shader::LogicOperation;
using Tegra::Shader::OpCode;
using Tegra::Shader::Register;
using Tegra::Shader::Sampler;
@ -759,6 +760,31 @@ private:
return (absolute_offset % SchedPeriod) == 0;
}
void WriteLogicOperation(Register dest, LogicOperation logic_op, const std::string& op_a,
const std::string& op_b) {
switch (logic_op) {
case LogicOperation::And: {
regs.SetRegisterToInteger(dest, true, 0, '(' + op_a + " & " + op_b + ')', 1, 1);
break;
}
case LogicOperation::Or: {
regs.SetRegisterToInteger(dest, true, 0, '(' + op_a + " | " + op_b + ')', 1, 1);
break;
}
case LogicOperation::Xor: {
regs.SetRegisterToInteger(dest, true, 0, '(' + op_a + " ^ " + op_b + ')', 1, 1);
break;
}
case LogicOperation::PassB: {
regs.SetRegisterToInteger(dest, true, 0, op_b, 1, 1);
break;
}
default:
NGLOG_CRITICAL(HW_GPU, "Unimplemented logic operation: {}", static_cast<u32>(logic_op));
UNREACHABLE();
}
}
/**
* Compiles a single instruction from Tegra to GLSL.
* @param offset the offset of the Tegra shader instruction.
@ -942,55 +968,6 @@ private:
break;
}
case OpCode::Type::Logic: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, true);
if (instr.alu.lop.invert_a)
op_a = "~(" + op_a + ')';
switch (opcode->GetId()) {
case OpCode::Id::LOP32I: {
u32 imm = static_cast<u32>(instr.alu.imm20_32.Value());
if (instr.alu.lop.invert_b)
imm = ~imm;
std::string op_b = std::to_string(imm);
switch (instr.alu.lop.operation) {
case Tegra::Shader::LogicOperation::And: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " & " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::Or: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " | " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::Xor: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " ^ " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::PassB: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_b, 1, 1);
break;
}
default:
NGLOG_CRITICAL(HW_GPU, "Unimplemented lop32i operation: {}",
static_cast<u32>(instr.alu.lop.operation.Value()));
UNREACHABLE();
}
break;
}
default: {
NGLOG_CRITICAL(HW_GPU, "Unhandled logic instruction: {}", opcode->GetName());
UNREACHABLE();
}
}
break;
}
case OpCode::Type::Shift: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, true);
@ -1036,17 +1013,26 @@ private:
case OpCode::Type::ArithmeticIntegerImmediate: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
if (instr.iadd32i.negate_a)
op_a = '-' + op_a;
std::string op_b = '(' + std::to_string(instr.alu.imm20_32.Value()) + ')';
std::string op_b = std::to_string(instr.alu.imm20_32.Value());
switch (opcode->GetId()) {
case OpCode::Id::IADD32I:
if (instr.iadd32i.negate_a)
op_a = "-(" + op_a + ')';
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1,
instr.iadd32i.saturate != 0);
break;
case OpCode::Id::LOP32I: {
if (instr.alu.lop32i.invert_a)
op_a = "~(" + op_a + ')';
if (instr.alu.lop32i.invert_b)
op_b = "~(" + op_b + ')';
WriteLogicOperation(instr.gpr0, instr.alu.lop32i.operation, op_a, op_b);
break;
}
default: {
NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticIntegerImmediate instruction: {}",
opcode->GetName());
@ -1057,12 +1043,7 @@ private:
}
case OpCode::Type::ArithmeticInteger: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
if (instr.alu_integer.negate_a)
op_a = '-' + op_a;
std::string op_b = instr.alu_integer.negate_b ? "-" : "";
std::string op_b;
if (instr.is_b_imm) {
op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
} else {
@ -1078,6 +1059,12 @@ private:
case OpCode::Id::IADD_C:
case OpCode::Id::IADD_R:
case OpCode::Id::IADD_IMM: {
if (instr.alu_integer.negate_a)
op_a = "-(" + op_a + ')';
if (instr.alu_integer.negate_b)
op_b = "-(" + op_b + ')';
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1,
instr.alu.saturate_d);
break;
@ -1085,12 +1072,33 @@ private:
case OpCode::Id::ISCADD_C:
case OpCode::Id::ISCADD_R:
case OpCode::Id::ISCADD_IMM: {
if (instr.alu_integer.negate_a)
op_a = "-(" + op_a + ')';
if (instr.alu_integer.negate_b)
op_b = "-(" + op_b + ')';
std::string shift = std::to_string(instr.alu_integer.shift_amount.Value());
regs.SetRegisterToInteger(instr.gpr0, true, 0,
"((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
break;
}
case OpCode::Id::LOP_C:
case OpCode::Id::LOP_R:
case OpCode::Id::LOP_IMM: {
ASSERT_MSG(!instr.alu.lop.unk44, "Unimplemented");
ASSERT_MSG(instr.alu.lop.pred48 == Pred::UnusedIndex, "Unimplemented");
if (instr.alu.lop.invert_a)
op_a = "~(" + op_a + ')';
if (instr.alu.lop.invert_b)
op_b = "~(" + op_b + ')';
WriteLogicOperation(instr.gpr0, instr.alu.lop.operation, op_a, op_b);
break;
}
default: {
NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticInteger instruction: {}",
opcode->GetName());