815 lines
28 KiB
C++
815 lines
28 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/environment.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#include "shader_recompiler/ir_opt/passes.h"
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#include "shader_recompiler/shader_info.h"
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namespace Shader::Optimization {
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namespace {
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void AddConstantBufferDescriptor(Info& info, u32 index, u32 count) {
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if (count != 1) {
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throw NotImplementedException("Constant buffer descriptor indexing");
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}
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if ((info.constant_buffer_mask & (1U << index)) != 0) {
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return;
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}
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info.constant_buffer_mask |= 1U << index;
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auto& cbufs{info.constant_buffer_descriptors};
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cbufs.insert(std::ranges::lower_bound(cbufs, index, {}, &ConstantBufferDescriptor::index),
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ConstantBufferDescriptor{
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.index = index,
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.count = 1,
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});
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}
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void GetAttribute(Info& info, IR::Attribute attribute) {
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if (IR::IsGeneric(attribute)) {
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info.input_generics.at(IR::GenericAttributeIndex(attribute)).used = true;
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return;
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}
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switch (attribute) {
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case IR::Attribute::PrimitiveId:
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info.loads_primitive_id = true;
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break;
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case IR::Attribute::PositionX:
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionW:
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info.loads_position = true;
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break;
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case IR::Attribute::InstanceId:
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info.loads_instance_id = true;
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break;
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case IR::Attribute::VertexId:
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info.loads_vertex_id = true;
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break;
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case IR::Attribute::FrontFace:
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info.loads_front_face = true;
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break;
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case IR::Attribute::PointSpriteS:
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case IR::Attribute::PointSpriteT:
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info.loads_point_coord = true;
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break;
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case IR::Attribute::TessellationEvaluationPointU:
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case IR::Attribute::TessellationEvaluationPointV:
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info.loads_tess_coord = true;
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break;
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default:
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throw NotImplementedException("Get attribute {}", attribute);
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}
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}
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void SetAttribute(Info& info, IR::Attribute attribute) {
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if (IR::IsGeneric(attribute)) {
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info.stores_generics.at(IR::GenericAttributeIndex(attribute)) = true;
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return;
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}
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switch (attribute) {
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case IR::Attribute::PointSize:
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info.stores_point_size = true;
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break;
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case IR::Attribute::PositionX:
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionW:
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info.stores_position = true;
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break;
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case IR::Attribute::ClipDistance0:
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case IR::Attribute::ClipDistance1:
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case IR::Attribute::ClipDistance2:
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case IR::Attribute::ClipDistance3:
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case IR::Attribute::ClipDistance4:
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case IR::Attribute::ClipDistance5:
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case IR::Attribute::ClipDistance6:
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case IR::Attribute::ClipDistance7:
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info.stores_clip_distance = true;
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break;
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case IR::Attribute::Layer:
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info.stores_layer = true;
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break;
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case IR::Attribute::ViewportIndex:
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info.stores_viewport_index = true;
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break;
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case IR::Attribute::ViewportMask:
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info.stores_viewport_mask = true;
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break;
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default:
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throw NotImplementedException("Set attribute {}", attribute);
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}
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}
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void GetPatch(Info& info, IR::Patch patch) {
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if (!IR::IsGeneric(patch)) {
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throw NotImplementedException("Reading non-generic patch {}", patch);
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}
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info.uses_patches.at(IR::GenericPatchIndex(patch)) = true;
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}
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void SetPatch(Info& info, IR::Patch patch) {
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if (IR::IsGeneric(patch)) {
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info.uses_patches.at(IR::GenericPatchIndex(patch)) = true;
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return;
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}
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switch (patch) {
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case IR::Patch::TessellationLodLeft:
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case IR::Patch::TessellationLodTop:
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case IR::Patch::TessellationLodRight:
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case IR::Patch::TessellationLodBottom:
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info.stores_tess_level_outer = true;
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break;
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case IR::Patch::TessellationLodInteriorU:
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case IR::Patch::TessellationLodInteriorV:
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info.stores_tess_level_inner = true;
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break;
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default:
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throw NotImplementedException("Set patch {}", patch);
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}
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}
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void VisitUsages(Info& info, IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::CompositeConstructF16x2:
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case IR::Opcode::CompositeConstructF16x3:
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case IR::Opcode::CompositeConstructF16x4:
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case IR::Opcode::CompositeExtractF16x2:
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case IR::Opcode::CompositeExtractF16x3:
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case IR::Opcode::CompositeExtractF16x4:
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case IR::Opcode::CompositeInsertF16x2:
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case IR::Opcode::CompositeInsertF16x3:
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case IR::Opcode::CompositeInsertF16x4:
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case IR::Opcode::SelectF16:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastF16U16:
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case IR::Opcode::PackFloat2x16:
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case IR::Opcode::UnpackFloat2x16:
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case IR::Opcode::ConvertS16F16:
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case IR::Opcode::ConvertS32F16:
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case IR::Opcode::ConvertS64F16:
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case IR::Opcode::ConvertU16F16:
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case IR::Opcode::ConvertU32F16:
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case IR::Opcode::ConvertU64F16:
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case IR::Opcode::ConvertF16S8:
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case IR::Opcode::ConvertF16S16:
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case IR::Opcode::ConvertF16S32:
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case IR::Opcode::ConvertF16S64:
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case IR::Opcode::ConvertF16U8:
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case IR::Opcode::ConvertF16U16:
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case IR::Opcode::ConvertF16U32:
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case IR::Opcode::ConvertF16U64:
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case IR::Opcode::FPAbs16:
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case IR::Opcode::FPAdd16:
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case IR::Opcode::FPCeil16:
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case IR::Opcode::FPFloor16:
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case IR::Opcode::FPFma16:
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case IR::Opcode::FPMul16:
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case IR::Opcode::FPNeg16:
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case IR::Opcode::FPRoundEven16:
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case IR::Opcode::FPSaturate16:
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case IR::Opcode::FPClamp16:
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case IR::Opcode::FPTrunc16:
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case IR::Opcode::FPOrdEqual16:
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case IR::Opcode::FPUnordEqual16:
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case IR::Opcode::FPOrdNotEqual16:
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case IR::Opcode::FPUnordNotEqual16:
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case IR::Opcode::FPOrdLessThan16:
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case IR::Opcode::FPUnordLessThan16:
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case IR::Opcode::FPOrdGreaterThan16:
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case IR::Opcode::FPUnordGreaterThan16:
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case IR::Opcode::FPOrdLessThanEqual16:
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case IR::Opcode::FPUnordLessThanEqual16:
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case IR::Opcode::FPOrdGreaterThanEqual16:
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case IR::Opcode::FPUnordGreaterThanEqual16:
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case IR::Opcode::FPIsNan16:
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case IR::Opcode::GlobalAtomicAddF16x2:
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case IR::Opcode::GlobalAtomicMinF16x2:
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case IR::Opcode::GlobalAtomicMaxF16x2:
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case IR::Opcode::StorageAtomicAddF16x2:
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case IR::Opcode::StorageAtomicMinF16x2:
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case IR::Opcode::StorageAtomicMaxF16x2:
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info.uses_fp16 = true;
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break;
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case IR::Opcode::CompositeConstructF64x2:
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case IR::Opcode::CompositeConstructF64x3:
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case IR::Opcode::CompositeConstructF64x4:
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case IR::Opcode::CompositeExtractF64x2:
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case IR::Opcode::CompositeExtractF64x3:
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case IR::Opcode::CompositeExtractF64x4:
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case IR::Opcode::CompositeInsertF64x2:
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case IR::Opcode::CompositeInsertF64x3:
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case IR::Opcode::CompositeInsertF64x4:
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case IR::Opcode::SelectF64:
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case IR::Opcode::BitCastU64F64:
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case IR::Opcode::BitCastF64U64:
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case IR::Opcode::PackDouble2x32:
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case IR::Opcode::UnpackDouble2x32:
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case IR::Opcode::FPAbs64:
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case IR::Opcode::FPAdd64:
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case IR::Opcode::FPCeil64:
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case IR::Opcode::FPFloor64:
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case IR::Opcode::FPFma64:
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case IR::Opcode::FPMax64:
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case IR::Opcode::FPMin64:
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case IR::Opcode::FPMul64:
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case IR::Opcode::FPNeg64:
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case IR::Opcode::FPRecip64:
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case IR::Opcode::FPRecipSqrt64:
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case IR::Opcode::FPRoundEven64:
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case IR::Opcode::FPSaturate64:
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case IR::Opcode::FPClamp64:
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case IR::Opcode::FPTrunc64:
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case IR::Opcode::FPOrdEqual64:
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case IR::Opcode::FPUnordEqual64:
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case IR::Opcode::FPOrdNotEqual64:
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case IR::Opcode::FPUnordNotEqual64:
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case IR::Opcode::FPOrdLessThan64:
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case IR::Opcode::FPUnordLessThan64:
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case IR::Opcode::FPOrdGreaterThan64:
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case IR::Opcode::FPUnordGreaterThan64:
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case IR::Opcode::FPOrdLessThanEqual64:
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case IR::Opcode::FPUnordLessThanEqual64:
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case IR::Opcode::FPOrdGreaterThanEqual64:
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case IR::Opcode::FPUnordGreaterThanEqual64:
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case IR::Opcode::FPIsNan64:
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case IR::Opcode::ConvertS16F64:
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case IR::Opcode::ConvertS32F64:
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case IR::Opcode::ConvertS64F64:
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case IR::Opcode::ConvertU16F64:
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case IR::Opcode::ConvertU32F64:
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case IR::Opcode::ConvertU64F64:
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case IR::Opcode::ConvertF32F64:
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case IR::Opcode::ConvertF64F32:
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case IR::Opcode::ConvertF64S8:
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case IR::Opcode::ConvertF64S16:
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case IR::Opcode::ConvertF64S32:
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case IR::Opcode::ConvertF64S64:
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case IR::Opcode::ConvertF64U8:
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case IR::Opcode::ConvertF64U16:
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case IR::Opcode::ConvertF64U32:
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case IR::Opcode::ConvertF64U64:
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info.uses_fp64 = true;
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break;
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default:
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::GetCbufU8:
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case IR::Opcode::GetCbufS8:
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case IR::Opcode::UndefU8:
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::WriteGlobalU8:
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case IR::Opcode::WriteGlobalS8:
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case IR::Opcode::LoadStorageU8:
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case IR::Opcode::LoadStorageS8:
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case IR::Opcode::WriteStorageU8:
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case IR::Opcode::WriteStorageS8:
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case IR::Opcode::LoadSharedU8:
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case IR::Opcode::LoadSharedS8:
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case IR::Opcode::WriteSharedU8:
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case IR::Opcode::SelectU8:
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case IR::Opcode::ConvertF16S8:
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case IR::Opcode::ConvertF16U8:
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case IR::Opcode::ConvertF32S8:
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case IR::Opcode::ConvertF32U8:
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case IR::Opcode::ConvertF64S8:
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case IR::Opcode::ConvertF64U8:
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info.uses_int8 = true;
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break;
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default:
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::GetCbufU16:
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case IR::Opcode::GetCbufS16:
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case IR::Opcode::UndefU16:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::WriteGlobalU16:
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case IR::Opcode::WriteGlobalS16:
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case IR::Opcode::LoadStorageU16:
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case IR::Opcode::LoadStorageS16:
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case IR::Opcode::WriteStorageU16:
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case IR::Opcode::WriteStorageS16:
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case IR::Opcode::LoadSharedU16:
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case IR::Opcode::LoadSharedS16:
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case IR::Opcode::WriteSharedU16:
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case IR::Opcode::SelectU16:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastF16U16:
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case IR::Opcode::ConvertS16F16:
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case IR::Opcode::ConvertS16F32:
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case IR::Opcode::ConvertS16F64:
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case IR::Opcode::ConvertU16F16:
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case IR::Opcode::ConvertU16F32:
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case IR::Opcode::ConvertU16F64:
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case IR::Opcode::ConvertF16S16:
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case IR::Opcode::ConvertF16U16:
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case IR::Opcode::ConvertF32S16:
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case IR::Opcode::ConvertF32U16:
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case IR::Opcode::ConvertF64S16:
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case IR::Opcode::ConvertF64U16:
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info.uses_int16 = true;
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break;
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default:
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::UndefU64:
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::LoadGlobal32:
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case IR::Opcode::LoadGlobal64:
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case IR::Opcode::LoadGlobal128:
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case IR::Opcode::WriteGlobalU8:
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case IR::Opcode::WriteGlobalS8:
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case IR::Opcode::WriteGlobalU16:
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case IR::Opcode::WriteGlobalS16:
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case IR::Opcode::WriteGlobal32:
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case IR::Opcode::WriteGlobal64:
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case IR::Opcode::WriteGlobal128:
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case IR::Opcode::SelectU64:
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case IR::Opcode::BitCastU64F64:
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case IR::Opcode::BitCastF64U64:
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case IR::Opcode::PackUint2x32:
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case IR::Opcode::UnpackUint2x32:
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case IR::Opcode::IAdd64:
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case IR::Opcode::ISub64:
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case IR::Opcode::INeg64:
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case IR::Opcode::ShiftLeftLogical64:
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case IR::Opcode::ShiftRightLogical64:
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case IR::Opcode::ShiftRightArithmetic64:
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case IR::Opcode::ConvertS64F16:
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case IR::Opcode::ConvertS64F32:
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case IR::Opcode::ConvertS64F64:
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case IR::Opcode::ConvertU64F16:
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case IR::Opcode::ConvertU64F32:
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case IR::Opcode::ConvertU64F64:
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case IR::Opcode::ConvertU64U32:
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case IR::Opcode::ConvertU32U64:
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case IR::Opcode::ConvertF16U64:
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case IR::Opcode::ConvertF32U64:
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case IR::Opcode::ConvertF64U64:
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case IR::Opcode::SharedAtomicExchange64:
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case IR::Opcode::GlobalAtomicIAdd64:
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case IR::Opcode::GlobalAtomicSMin64:
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case IR::Opcode::GlobalAtomicUMin64:
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case IR::Opcode::GlobalAtomicSMax64:
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case IR::Opcode::GlobalAtomicUMax64:
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case IR::Opcode::GlobalAtomicAnd64:
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case IR::Opcode::GlobalAtomicOr64:
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case IR::Opcode::GlobalAtomicXor64:
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case IR::Opcode::GlobalAtomicExchange64:
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case IR::Opcode::StorageAtomicIAdd64:
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case IR::Opcode::StorageAtomicSMin64:
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case IR::Opcode::StorageAtomicUMin64:
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case IR::Opcode::StorageAtomicSMax64:
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case IR::Opcode::StorageAtomicUMax64:
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case IR::Opcode::StorageAtomicAnd64:
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case IR::Opcode::StorageAtomicOr64:
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case IR::Opcode::StorageAtomicXor64:
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case IR::Opcode::StorageAtomicExchange64:
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info.uses_int64 = true;
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break;
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default:
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::LoadGlobal32:
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case IR::Opcode::LoadGlobal64:
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case IR::Opcode::LoadGlobal128:
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case IR::Opcode::WriteGlobalU8:
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case IR::Opcode::WriteGlobalS8:
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case IR::Opcode::WriteGlobalU16:
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case IR::Opcode::WriteGlobalS16:
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case IR::Opcode::WriteGlobal32:
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case IR::Opcode::WriteGlobal64:
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case IR::Opcode::WriteGlobal128:
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case IR::Opcode::GlobalAtomicIAdd32:
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case IR::Opcode::GlobalAtomicSMin32:
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case IR::Opcode::GlobalAtomicUMin32:
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case IR::Opcode::GlobalAtomicSMax32:
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case IR::Opcode::GlobalAtomicUMax32:
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case IR::Opcode::GlobalAtomicInc32:
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case IR::Opcode::GlobalAtomicDec32:
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case IR::Opcode::GlobalAtomicAnd32:
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case IR::Opcode::GlobalAtomicOr32:
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case IR::Opcode::GlobalAtomicXor32:
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case IR::Opcode::GlobalAtomicExchange32:
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case IR::Opcode::GlobalAtomicIAdd64:
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case IR::Opcode::GlobalAtomicSMin64:
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case IR::Opcode::GlobalAtomicUMin64:
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case IR::Opcode::GlobalAtomicSMax64:
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case IR::Opcode::GlobalAtomicUMax64:
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case IR::Opcode::GlobalAtomicAnd64:
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case IR::Opcode::GlobalAtomicOr64:
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case IR::Opcode::GlobalAtomicXor64:
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case IR::Opcode::GlobalAtomicExchange64:
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case IR::Opcode::GlobalAtomicAddF32:
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case IR::Opcode::GlobalAtomicAddF16x2:
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case IR::Opcode::GlobalAtomicAddF32x2:
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case IR::Opcode::GlobalAtomicMinF16x2:
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case IR::Opcode::GlobalAtomicMinF32x2:
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case IR::Opcode::GlobalAtomicMaxF16x2:
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case IR::Opcode::GlobalAtomicMaxF32x2:
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info.uses_int64 = true;
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info.uses_global_memory = true;
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info.used_constant_buffer_types |= IR::Type::U32 | IR::Type::U32x2;
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info.used_storage_buffer_types |= IR::Type::U32 | IR::Type::U32x2 | IR::Type::U32x4;
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break;
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default:
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::DemoteToHelperInvocation:
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info.uses_demote_to_helper_invocation = true;
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break;
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case IR::Opcode::GetAttribute:
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GetAttribute(info, inst.Arg(0).Attribute());
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break;
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case IR::Opcode::SetAttribute:
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SetAttribute(info, inst.Arg(0).Attribute());
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break;
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case IR::Opcode::GetPatch:
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GetPatch(info, inst.Arg(0).Patch());
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break;
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case IR::Opcode::SetPatch:
|
|
SetPatch(info, inst.Arg(0).Patch());
|
|
break;
|
|
case IR::Opcode::GetAttributeIndexed:
|
|
info.loads_indexed_attributes = true;
|
|
break;
|
|
case IR::Opcode::SetAttributeIndexed:
|
|
info.stores_indexed_attributes = true;
|
|
break;
|
|
case IR::Opcode::SetFragColor:
|
|
info.stores_frag_color[inst.Arg(0).U32()] = true;
|
|
break;
|
|
case IR::Opcode::SetSampleMask:
|
|
info.stores_sample_mask = true;
|
|
break;
|
|
case IR::Opcode::SetFragDepth:
|
|
info.stores_frag_depth = true;
|
|
break;
|
|
case IR::Opcode::WorkgroupId:
|
|
info.uses_workgroup_id = true;
|
|
break;
|
|
case IR::Opcode::LocalInvocationId:
|
|
info.uses_local_invocation_id = true;
|
|
break;
|
|
case IR::Opcode::InvocationId:
|
|
info.uses_invocation_id = true;
|
|
break;
|
|
case IR::Opcode::SampleId:
|
|
info.uses_sample_id = true;
|
|
break;
|
|
case IR::Opcode::IsHelperInvocation:
|
|
info.uses_is_helper_invocation = true;
|
|
break;
|
|
case IR::Opcode::LaneId:
|
|
case IR::Opcode::ShuffleIndex:
|
|
case IR::Opcode::ShuffleUp:
|
|
case IR::Opcode::ShuffleDown:
|
|
case IR::Opcode::ShuffleButterfly:
|
|
info.uses_subgroup_invocation_id = true;
|
|
break;
|
|
case IR::Opcode::GetCbufU8:
|
|
case IR::Opcode::GetCbufS8:
|
|
case IR::Opcode::GetCbufU16:
|
|
case IR::Opcode::GetCbufS16:
|
|
case IR::Opcode::GetCbufU32:
|
|
case IR::Opcode::GetCbufF32:
|
|
case IR::Opcode::GetCbufU32x2: {
|
|
if (const IR::Value index{inst.Arg(0)}; index.IsImmediate()) {
|
|
AddConstantBufferDescriptor(info, index.U32(), 1);
|
|
} else {
|
|
throw NotImplementedException("Constant buffer with non-immediate index");
|
|
}
|
|
switch (inst.GetOpcode()) {
|
|
case IR::Opcode::GetCbufU8:
|
|
case IR::Opcode::GetCbufS8:
|
|
info.used_constant_buffer_types |= IR::Type::U8;
|
|
break;
|
|
case IR::Opcode::GetCbufU16:
|
|
case IR::Opcode::GetCbufS16:
|
|
info.used_constant_buffer_types |= IR::Type::U16;
|
|
break;
|
|
case IR::Opcode::GetCbufU32:
|
|
info.used_constant_buffer_types |= IR::Type::U32;
|
|
break;
|
|
case IR::Opcode::GetCbufF32:
|
|
info.used_constant_buffer_types |= IR::Type::F32;
|
|
break;
|
|
case IR::Opcode::GetCbufU32x2:
|
|
info.used_constant_buffer_types |= IR::Type::U32x2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case IR::Opcode::BindlessImageSampleImplicitLod:
|
|
case IR::Opcode::BindlessImageSampleExplicitLod:
|
|
case IR::Opcode::BindlessImageSampleDrefImplicitLod:
|
|
case IR::Opcode::BindlessImageSampleDrefExplicitLod:
|
|
case IR::Opcode::BindlessImageGather:
|
|
case IR::Opcode::BindlessImageGatherDref:
|
|
case IR::Opcode::BindlessImageFetch:
|
|
case IR::Opcode::BindlessImageQueryDimensions:
|
|
case IR::Opcode::BindlessImageQueryLod:
|
|
case IR::Opcode::BindlessImageGradient:
|
|
case IR::Opcode::BoundImageSampleImplicitLod:
|
|
case IR::Opcode::BoundImageSampleExplicitLod:
|
|
case IR::Opcode::BoundImageSampleDrefImplicitLod:
|
|
case IR::Opcode::BoundImageSampleDrefExplicitLod:
|
|
case IR::Opcode::BoundImageGather:
|
|
case IR::Opcode::BoundImageGatherDref:
|
|
case IR::Opcode::BoundImageFetch:
|
|
case IR::Opcode::BoundImageQueryDimensions:
|
|
case IR::Opcode::BoundImageQueryLod:
|
|
case IR::Opcode::BoundImageGradient:
|
|
case IR::Opcode::ImageSampleImplicitLod:
|
|
case IR::Opcode::ImageSampleExplicitLod:
|
|
case IR::Opcode::ImageSampleDrefImplicitLod:
|
|
case IR::Opcode::ImageSampleDrefExplicitLod:
|
|
case IR::Opcode::ImageGather:
|
|
case IR::Opcode::ImageGatherDref:
|
|
case IR::Opcode::ImageFetch:
|
|
case IR::Opcode::ImageQueryDimensions:
|
|
case IR::Opcode::ImageQueryLod:
|
|
case IR::Opcode::ImageGradient: {
|
|
const TextureType type{inst.Flags<IR::TextureInstInfo>().type};
|
|
info.uses_sampled_1d |= type == TextureType::Color1D || type == TextureType::ColorArray1D;
|
|
info.uses_sparse_residency |=
|
|
inst.GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp) != nullptr;
|
|
break;
|
|
}
|
|
case IR::Opcode::ImageRead: {
|
|
const auto flags{inst.Flags<IR::TextureInstInfo>()};
|
|
info.uses_typeless_image_reads |= flags.image_format == ImageFormat::Typeless;
|
|
info.uses_sparse_residency |=
|
|
inst.GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp) != nullptr;
|
|
break;
|
|
}
|
|
case IR::Opcode::ImageWrite: {
|
|
const auto flags{inst.Flags<IR::TextureInstInfo>()};
|
|
info.uses_typeless_image_writes |= flags.image_format == ImageFormat::Typeless;
|
|
break;
|
|
}
|
|
case IR::Opcode::SubgroupEqMask:
|
|
case IR::Opcode::SubgroupLtMask:
|
|
case IR::Opcode::SubgroupLeMask:
|
|
case IR::Opcode::SubgroupGtMask:
|
|
case IR::Opcode::SubgroupGeMask:
|
|
info.uses_subgroup_mask = true;
|
|
break;
|
|
case IR::Opcode::VoteAll:
|
|
case IR::Opcode::VoteAny:
|
|
case IR::Opcode::VoteEqual:
|
|
case IR::Opcode::SubgroupBallot:
|
|
info.uses_subgroup_vote = true;
|
|
break;
|
|
case IR::Opcode::FSwizzleAdd:
|
|
info.uses_fswzadd = true;
|
|
break;
|
|
case IR::Opcode::DPdxFine:
|
|
case IR::Opcode::DPdyFine:
|
|
case IR::Opcode::DPdxCoarse:
|
|
case IR::Opcode::DPdyCoarse:
|
|
info.uses_derivatives = true;
|
|
break;
|
|
case IR::Opcode::LoadStorageU8:
|
|
case IR::Opcode::LoadStorageS8:
|
|
case IR::Opcode::WriteStorageU8:
|
|
case IR::Opcode::WriteStorageS8:
|
|
info.used_storage_buffer_types |= IR::Type::U8;
|
|
break;
|
|
case IR::Opcode::LoadStorageU16:
|
|
case IR::Opcode::LoadStorageS16:
|
|
case IR::Opcode::WriteStorageU16:
|
|
case IR::Opcode::WriteStorageS16:
|
|
info.used_storage_buffer_types |= IR::Type::U16;
|
|
break;
|
|
case IR::Opcode::LoadStorage32:
|
|
case IR::Opcode::WriteStorage32:
|
|
case IR::Opcode::StorageAtomicIAdd32:
|
|
case IR::Opcode::StorageAtomicSMin32:
|
|
case IR::Opcode::StorageAtomicUMin32:
|
|
case IR::Opcode::StorageAtomicSMax32:
|
|
case IR::Opcode::StorageAtomicUMax32:
|
|
case IR::Opcode::StorageAtomicAnd32:
|
|
case IR::Opcode::StorageAtomicOr32:
|
|
case IR::Opcode::StorageAtomicXor32:
|
|
case IR::Opcode::StorageAtomicExchange32:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
break;
|
|
case IR::Opcode::LoadStorage64:
|
|
case IR::Opcode::WriteStorage64:
|
|
info.used_storage_buffer_types |= IR::Type::U32x2;
|
|
break;
|
|
case IR::Opcode::LoadStorage128:
|
|
case IR::Opcode::WriteStorage128:
|
|
info.used_storage_buffer_types |= IR::Type::U32x4;
|
|
break;
|
|
case IR::Opcode::SharedAtomicInc32:
|
|
info.uses_shared_increment = true;
|
|
break;
|
|
case IR::Opcode::SharedAtomicDec32:
|
|
info.uses_shared_decrement = true;
|
|
break;
|
|
case IR::Opcode::SharedAtomicExchange64:
|
|
info.uses_int64_bit_atomics = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicInc32:
|
|
case IR::Opcode::StorageAtomicInc32:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_global_increment = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicDec32:
|
|
case IR::Opcode::StorageAtomicDec32:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_global_decrement = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicAddF32:
|
|
case IR::Opcode::StorageAtomicAddF32:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_atomic_f32_add = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicAddF16x2:
|
|
case IR::Opcode::StorageAtomicAddF16x2:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_atomic_f16x2_add = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicAddF32x2:
|
|
case IR::Opcode::StorageAtomicAddF32x2:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_atomic_f32x2_add = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicMinF16x2:
|
|
case IR::Opcode::StorageAtomicMinF16x2:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_atomic_f16x2_min = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicMinF32x2:
|
|
case IR::Opcode::StorageAtomicMinF32x2:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_atomic_f32x2_min = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicMaxF16x2:
|
|
case IR::Opcode::StorageAtomicMaxF16x2:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_atomic_f16x2_max = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicMaxF32x2:
|
|
case IR::Opcode::StorageAtomicMaxF32x2:
|
|
info.used_storage_buffer_types |= IR::Type::U32;
|
|
info.uses_atomic_f32x2_max = true;
|
|
break;
|
|
case IR::Opcode::GlobalAtomicIAdd64:
|
|
case IR::Opcode::GlobalAtomicSMin64:
|
|
case IR::Opcode::GlobalAtomicUMin64:
|
|
case IR::Opcode::GlobalAtomicSMax64:
|
|
case IR::Opcode::GlobalAtomicUMax64:
|
|
case IR::Opcode::GlobalAtomicAnd64:
|
|
case IR::Opcode::GlobalAtomicOr64:
|
|
case IR::Opcode::GlobalAtomicXor64:
|
|
case IR::Opcode::GlobalAtomicExchange64:
|
|
case IR::Opcode::StorageAtomicIAdd64:
|
|
case IR::Opcode::StorageAtomicSMin64:
|
|
case IR::Opcode::StorageAtomicUMin64:
|
|
case IR::Opcode::StorageAtomicSMax64:
|
|
case IR::Opcode::StorageAtomicUMax64:
|
|
case IR::Opcode::StorageAtomicAnd64:
|
|
case IR::Opcode::StorageAtomicOr64:
|
|
case IR::Opcode::StorageAtomicXor64:
|
|
info.used_storage_buffer_types |= IR::Type::U64;
|
|
info.uses_int64_bit_atomics = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void VisitFpModifiers(Info& info, IR::Inst& inst) {
|
|
switch (inst.GetOpcode()) {
|
|
case IR::Opcode::FPAdd16:
|
|
case IR::Opcode::FPFma16:
|
|
case IR::Opcode::FPMul16:
|
|
case IR::Opcode::FPRoundEven16:
|
|
case IR::Opcode::FPFloor16:
|
|
case IR::Opcode::FPCeil16:
|
|
case IR::Opcode::FPTrunc16: {
|
|
const auto control{inst.Flags<IR::FpControl>()};
|
|
switch (control.fmz_mode) {
|
|
case IR::FmzMode::DontCare:
|
|
break;
|
|
case IR::FmzMode::FTZ:
|
|
case IR::FmzMode::FMZ:
|
|
info.uses_fp16_denorms_flush = true;
|
|
break;
|
|
case IR::FmzMode::None:
|
|
info.uses_fp16_denorms_preserve = true;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case IR::Opcode::FPAdd32:
|
|
case IR::Opcode::FPFma32:
|
|
case IR::Opcode::FPMul32:
|
|
case IR::Opcode::FPRoundEven32:
|
|
case IR::Opcode::FPFloor32:
|
|
case IR::Opcode::FPCeil32:
|
|
case IR::Opcode::FPTrunc32:
|
|
case IR::Opcode::FPOrdEqual32:
|
|
case IR::Opcode::FPUnordEqual32:
|
|
case IR::Opcode::FPOrdNotEqual32:
|
|
case IR::Opcode::FPUnordNotEqual32:
|
|
case IR::Opcode::FPOrdLessThan32:
|
|
case IR::Opcode::FPUnordLessThan32:
|
|
case IR::Opcode::FPOrdGreaterThan32:
|
|
case IR::Opcode::FPUnordGreaterThan32:
|
|
case IR::Opcode::FPOrdLessThanEqual32:
|
|
case IR::Opcode::FPUnordLessThanEqual32:
|
|
case IR::Opcode::FPOrdGreaterThanEqual32:
|
|
case IR::Opcode::FPUnordGreaterThanEqual32:
|
|
case IR::Opcode::ConvertF16F32:
|
|
case IR::Opcode::ConvertF64F32: {
|
|
const auto control{inst.Flags<IR::FpControl>()};
|
|
switch (control.fmz_mode) {
|
|
case IR::FmzMode::DontCare:
|
|
break;
|
|
case IR::FmzMode::FTZ:
|
|
case IR::FmzMode::FMZ:
|
|
info.uses_fp32_denorms_flush = true;
|
|
break;
|
|
case IR::FmzMode::None:
|
|
info.uses_fp32_denorms_preserve = true;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Visit(Info& info, IR::Inst& inst) {
|
|
VisitUsages(info, inst);
|
|
VisitFpModifiers(info, inst);
|
|
}
|
|
|
|
void GatherInfoFromHeader(Environment& env, Info& info) {
|
|
Stage stage{env.ShaderStage()};
|
|
if (stage == Stage::Compute) {
|
|
return;
|
|
}
|
|
const auto& header{env.SPH()};
|
|
if (stage == Stage::Fragment) {
|
|
if (!info.loads_indexed_attributes) {
|
|
return;
|
|
}
|
|
for (size_t i = 0; i < info.input_generics.size(); i++) {
|
|
info.input_generics[i].used |= header.ps.IsGenericVectorActive(i);
|
|
}
|
|
info.loads_position |= header.ps.imap_systemb.position != 0;
|
|
return;
|
|
}
|
|
if (info.loads_indexed_attributes) {
|
|
for (size_t i = 0; i < info.input_generics.size(); i++) {
|
|
info.input_generics[i].used |= header.vtg.IsInputGenericVectorActive(i);
|
|
}
|
|
info.loads_position |= header.vtg.imap_systemb.position != 0;
|
|
}
|
|
if (info.stores_indexed_attributes) {
|
|
for (size_t i = 0; i < info.stores_generics.size(); i++) {
|
|
info.stores_generics[i] |= header.vtg.IsOutputGenericVectorActive(i);
|
|
}
|
|
info.stores_clip_distance |= header.vtg.omap_systemc.clip_distances != 0;
|
|
info.stores_position |= header.vtg.omap_systemb.position != 0;
|
|
}
|
|
}
|
|
} // Anonymous namespace
|
|
|
|
void CollectShaderInfoPass(Environment& env, IR::Program& program) {
|
|
Info& info{program.info};
|
|
for (IR::Block* const block : program.post_order_blocks) {
|
|
for (IR::Inst& inst : block->Instructions()) {
|
|
Visit(info, inst);
|
|
}
|
|
}
|
|
GatherInfoFromHeader(env, info);
|
|
}
|
|
|
|
} // namespace Shader::Optimization
|