255 lines
7.4 KiB
C
255 lines
7.4 KiB
C
/*
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armmmu.c - Memory Management Unit emulation.
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ARMulator extensions for the ARM7100 family.
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Copyright (C) 1999 Ben Williamson
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ARMMMU_H_
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#define _ARMMMU_H_
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#define WORD_SHT 2
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#define WORD_SIZE (1<<WORD_SHT)
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/* The MMU is accessible with MCR and MRC operations to copro 15: */
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#define MMU_COPRO (15)
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/* Register numbers in the MMU: */
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typedef enum mmu_regnum_t
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{
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MMU_ID = 0,
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MMU_CONTROL = 1,
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MMU_TRANSLATION_TABLE_BASE = 2,
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MMU_DOMAIN_ACCESS_CONTROL = 3,
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MMU_FAULT_STATUS = 5,
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MMU_FAULT_ADDRESS = 6,
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MMU_CACHE_OPS = 7,
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MMU_TLB_OPS = 8,
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MMU_CACHE_LOCKDOWN = 9,
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MMU_TLB_LOCKDOWN = 10,
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MMU_PID = 13,
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/*MMU_V4 */
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MMU_V4_CACHE_OPS = 7,
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MMU_V4_TLB_OPS = 8,
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/*MMU_V3 */
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MMU_V3_FLUSH_TLB = 5,
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MMU_V3_FLUSH_TLB_ENTRY = 6,
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MMU_V3_FLUSH_CACHE = 7,
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/*MMU Intel SA-1100 */
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MMU_SA_RB_OPS = 9,
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MMU_SA_DEBUG = 14,
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MMU_SA_CP15_R15 = 15,
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//chy 2003-08-24
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/*Intel xscale CP15 */
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XSCALE_CP15_CACHE_TYPE = 0,
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XSCALE_CP15_AUX_CONTROL = 1,
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XSCALE_CP15_COPRO_ACCESS = 15,
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} mmu_regnum_t;
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/* Bits in the control register */
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#define CONTROL_MMU (1<<0)
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#define CONTROL_ALIGN_FAULT (1<<1)
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#define CONTROL_CACHE (1<<2)
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#define CONTROL_DATA_CACHE (1<<2)
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#define CONTROL_WRITE_BUFFER (1<<3)
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#define CONTROL_BIG_ENDIAN (1<<7)
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#define CONTROL_SYSTEM (1<<8)
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#define CONTROL_ROM (1<<9)
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#define CONTROL_UNDEFINED (1<<10)
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#define CONTROL_BRANCH_PREDICT (1<<11)
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#define CONTROL_INSTRUCTION_CACHE (1<<12)
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#define CONTROL_VECTOR (1<<13)
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#define CONTROL_RR (1<<14)
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#define CONTROL_L4 (1<<15)
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#define CONTROL_XP (1<<23)
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#define CONTROL_EE (1<<25)
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/*Macro defines for MMU state*/
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#define MMU_CTL (state->mmu.control)
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#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
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#define MMU_Disabled (!(MMU_Enabled))
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#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)
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#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
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#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))
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#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
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#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))
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#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
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#define MMU_CacheDisabled (!(MMU_CacheEnabled))
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#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
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#define MMU_WBDisabled (!(MMU_WBEnabled))
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/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
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#define PID_VA_MAP_MASK 0xfe000000
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//#define mmu_pid_va_map(va) ({\
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// ARMword ret; \
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// if ((va) & PID_VA_MAP_MASK)\
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// ret = (va); \
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// else \
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// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
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// ret;\
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//})
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#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
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/* FS[3:0] in the fault status register: */
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typedef enum fault_t
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{
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NO_FAULT = 0x0,
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ALIGNMENT_FAULT = 0x1,
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SECTION_TRANSLATION_FAULT = 0x5,
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PAGE_TRANSLATION_FAULT = 0x7,
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SECTION_DOMAIN_FAULT = 0x9,
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PAGE_DOMAIN_FAULT = 0xB,
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SECTION_PERMISSION_FAULT = 0xD,
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SUBPAGE_PERMISSION_FAULT = 0xF,
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/* defined by skyeye */
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TLB_READ_MISS = 0x30,
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TLB_WRITE_MISS = 0x40,
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} fault_t;
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typedef struct mmu_ops_s
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{
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/*initilization */
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int (*init) (ARMul_State * state);
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/*free on exit */
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void (*exit) (ARMul_State * state);
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/*read byte data */
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fault_t (*read_byte) (ARMul_State * state, ARMword va,
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ARMword * data);
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/*write byte data */
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fault_t (*write_byte) (ARMul_State * state, ARMword va,
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ARMword data);
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/*read halfword data */
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fault_t (*read_halfword) (ARMul_State * state, ARMword va,
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ARMword * data);
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/*write halfword data */
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fault_t (*write_halfword) (ARMul_State * state, ARMword va,
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ARMword data);
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/*read word data */
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fault_t (*read_word) (ARMul_State * state, ARMword va,
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ARMword * data);
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/*write word data */
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fault_t (*write_word) (ARMul_State * state, ARMword va,
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ARMword data);
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/*load instr */
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fault_t (*load_instr) (ARMul_State * state, ARMword va,
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ARMword * instr);
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/*mcr */
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ARMword (*mcr) (ARMul_State * state, ARMword instr, ARMword val);
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/*mrc */
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ARMword (*mrc) (ARMul_State * state, ARMword instr, ARMword * val);
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/*ywc 2005-04-16 convert virtual address to physics address */
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int (*v2p_dbct) (ARMul_State * state, ARMword virt_addr,
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ARMword * phys_addr);
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} mmu_ops_t;
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#include "core/arm/interpreter/mmu/tlb.h"
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#include "core/arm/interpreter/mmu/rb.h"
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#include "core/arm/interpreter/mmu/wb.h"
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#include "core/arm/interpreter/mmu/cache.h"
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/*special process mmu.h*/
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#include "core/arm/interpreter/mmu/sa_mmu.h"
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//#include "core/arm/interpreter/mmu/arm7100_mmu.h"
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//#include "core/arm/interpreter/mmu/arm920t_mmu.h"
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//#include "core/arm/interpreter/mmu/arm926ejs_mmu.h"
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#include "core/arm/interpreter/mmu/arm1176jzf_s_mmu.h"
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//#include "core/arm/interpreter/mmu/cortex_a9_mmu.h"
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typedef struct mmu_state_t
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{
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ARMword control;
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ARMword translation_table_base;
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/* dyf 201-08-11 for arm1176 */
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ARMword auxiliary_control;
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ARMword coprocessor_access_control;
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ARMword translation_table_base0;
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ARMword translation_table_base1;
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ARMword translation_table_ctrl;
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/* arm1176 end */
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ARMword domain_access_control;
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ARMword fault_status;
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ARMword fault_statusi; /* prefetch fault status */
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ARMword fault_address;
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ARMword last_domain;
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ARMword process_id;
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ARMword context_id;
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ARMword thread_uro_id;
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ARMword cache_locked_down;
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ARMword tlb_locked_down;
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//chy 2003-08-24 for xscale
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ARMword cache_type; // 0
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ARMword aux_control; // 1
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ARMword copro_access; // 15
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mmu_ops_t ops;
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union
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{
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sa_mmu_t sa_mmu;
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//arm7100_mmu_t arm7100_mmu;
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//arm920t_mmu_t arm920t_mmu;
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//arm926ejs_mmu_t arm926ejs_mmu;
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} u;
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} mmu_state_t;
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int mmu_init (ARMul_State * state);
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int mmu_reset (ARMul_State * state);
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void mmu_exit (ARMul_State * state);
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fault_t mmu_read_word (ARMul_State * state, ARMword virt_addr,
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ARMword * data);
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fault_t mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data);
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fault_t mmu_load_instr (ARMul_State * state, ARMword virt_addr,
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ARMword * instr);
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ARMword mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value);
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void mmu_mcr (ARMul_State * state, ARMword instr, ARMword value);
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/*ywc 20050416*/
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int mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr,
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ARMword * phys_addr);
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fault_t
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mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data);
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fault_t
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mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data);
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fault_t
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mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data);
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fault_t
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mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data);
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fault_t
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mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data);
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fault_t
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mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data);
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#endif /* _ARMMMU_H_ */
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