282 lines
8.6 KiB
C++
282 lines
8.6 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include "common/common_types.h"
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#include "common/bit_field.h"
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namespace GPU {
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// Returns index corresponding to the Regs member labeled by field_name
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// TODO: Due to Visual studio bug 209229, offsetof does not return constant expressions
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// when used with array elements (e.g. GPU_REG_INDEX(memory_fill_config[0])).
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// For details cf. https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
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// Hopefully, this will be fixed sometime in the future.
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// For lack of better alternatives, we currently hardcode the offsets when constant
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// expressions are needed via GPU_REG_INDEX_WORKAROUND (on sane compilers, static_asserts
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// will then make sure the offsets indeed match the automatically calculated ones).
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#define GPU_REG_INDEX(field_name) (offsetof(GPU::Regs, field_name) / sizeof(u32))
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#if defined(_MSC_VER)
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#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) (backup_workaround_index)
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#else
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// NOTE: Yeah, hacking in a static_assert here just to workaround the lacking MSVC compiler
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// really is this annoying. This macro just forwards its first argument to GPU_REG_INDEX
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// and then performs a (no-op) cast to size_t iff the second argument matches the expected
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// field offset. Otherwise, the compiler will fail to compile this code.
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#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
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((typename std::enable_if<backup_workaround_index == GPU_REG_INDEX(field_name), size_t>::type)GPU_REG_INDEX(field_name))
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#endif
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// MMIO region 0x1EFxxxxx
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struct Regs {
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// helper macro to properly align structure members.
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// Calling INSERT_PADDING_WORDS will add a new member variable with a name like "pad121",
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// depending on the current source line to make sure variable names are unique.
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#define INSERT_PADDING_WORDS_HELPER1(x, y) x ## y
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#define INSERT_PADDING_WORDS_HELPER2(x, y) INSERT_PADDING_WORDS_HELPER1(x, y)
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#define INSERT_PADDING_WORDS(num_words) u32 INSERT_PADDING_WORDS_HELPER2(pad, __LINE__)[(num_words)]
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// helper macro to make sure the defined structures are of the expected size.
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#if defined(_MSC_VER)
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// TODO: MSVC does not support using sizeof() on non-static data members even though this
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// is technically allowed since C++11. This macro should be enabled once MSVC adds
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// support for that.
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#define ASSERT_MEMBER_SIZE(name, size_in_bytes)
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#else
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#define ASSERT_MEMBER_SIZE(name, size_in_bytes) \
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static_assert(sizeof(name) == size_in_bytes, \
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"Structure size and register block length don't match")
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#endif
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// All of those formats are described in reverse byte order, since the 3DS is little-endian.
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enum class PixelFormat : u32 {
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RGBA8 = 0,
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RGB8 = 1,
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RGB565 = 2,
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RGB5A1 = 3,
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RGBA4 = 4,
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};
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/**
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* Returns the number of bytes per pixel.
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*/
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static int BytesPerPixel(PixelFormat format) {
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switch (format) {
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case PixelFormat::RGBA8:
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return 4;
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case PixelFormat::RGB8:
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return 3;
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case PixelFormat::RGB565:
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case PixelFormat::RGB5A1:
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case PixelFormat::RGBA4:
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return 2;
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default:
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UNIMPLEMENTED();
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}
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}
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INSERT_PADDING_WORDS(0x4);
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struct {
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u32 address_start;
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u32 address_end; // ?
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u32 size;
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u32 value; // ?
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inline u32 GetStartAddress() const {
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return DecodeAddressRegister(address_start);
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}
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inline u32 GetEndAddress() const {
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return DecodeAddressRegister(address_end);
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}
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} memory_fill_config[2];
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ASSERT_MEMBER_SIZE(memory_fill_config[0], 0x10);
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INSERT_PADDING_WORDS(0x10b);
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struct FramebufferConfig {
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union {
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u32 size;
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BitField< 0, 16, u32> width;
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BitField<16, 16, u32> height;
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};
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INSERT_PADDING_WORDS(0x2);
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u32 address_left1;
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u32 address_left2;
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union {
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u32 format;
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BitField< 0, 3, PixelFormat> color_format;
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};
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INSERT_PADDING_WORDS(0x1);
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union {
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u32 active_fb;
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// 0: Use parameters ending with "1"
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// 1: Use parameters ending with "2"
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BitField<0, 1, u32> second_fb_active;
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};
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INSERT_PADDING_WORDS(0x5);
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// Distance between two pixel rows, in bytes
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u32 stride;
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u32 address_right1;
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u32 address_right2;
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INSERT_PADDING_WORDS(0x30);
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} framebuffer_config[2];
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ASSERT_MEMBER_SIZE(framebuffer_config[0], 0x100);
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INSERT_PADDING_WORDS(0x169);
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struct {
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u32 input_address;
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u32 output_address;
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inline u32 GetPhysicalInputAddress() const {
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return DecodeAddressRegister(input_address);
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}
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inline u32 GetPhysicalOutputAddress() const {
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return DecodeAddressRegister(output_address);
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}
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union {
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u32 output_size;
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BitField< 0, 16, u32> output_width;
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BitField<16, 16, u32> output_height;
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};
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union {
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u32 input_size;
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BitField< 0, 16, u32> input_width;
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BitField<16, 16, u32> input_height;
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};
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union {
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u32 flags;
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BitField< 0, 1, u32> flip_data; // flips input data horizontally (TODO) if true
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BitField< 8, 3, PixelFormat> input_format;
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BitField<12, 3, PixelFormat> output_format;
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BitField<16, 1, u32> output_tiled; // stores output in a tiled format
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// TODO: Not really sure if this actually scales, or even resizes at all.
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BitField<24, 1, u32> scale_horizontally;
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};
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INSERT_PADDING_WORDS(0x1);
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// it seems that writing to this field triggers the display transfer
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u32 trigger;
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} display_transfer_config;
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ASSERT_MEMBER_SIZE(display_transfer_config, 0x1c);
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INSERT_PADDING_WORDS(0x331);
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struct {
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// command list size (in bytes)
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u32 size;
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INSERT_PADDING_WORDS(0x1);
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// command list address
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u32 address;
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INSERT_PADDING_WORDS(0x1);
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// it seems that writing to this field triggers command list processing
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u32 trigger;
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inline u32 GetPhysicalAddress() const {
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return DecodeAddressRegister(address);
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}
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} command_processor_config;
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ASSERT_MEMBER_SIZE(command_processor_config, 0x14);
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INSERT_PADDING_WORDS(0x9c3);
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#undef INSERT_PADDING_WORDS_HELPER1
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#undef INSERT_PADDING_WORDS_HELPER2
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#undef INSERT_PADDING_WORDS
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static inline size_t NumIds() {
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return sizeof(Regs) / sizeof(u32);
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}
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u32& operator [] (int index) const {
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u32* content = (u32*)this;
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return content[index];
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}
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u32& operator [] (int index) {
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u32* content = (u32*)this;
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return content[index];
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}
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private:
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/*
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* Most physical addresses which GPU registers refer to are 8-byte aligned.
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* This function should be used to get the address from a raw register value.
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*/
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static inline u32 DecodeAddressRegister(u32 register_value) {
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return register_value * 8;
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}
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};
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static_assert(std::is_standard_layout<Regs>::value, "Structure does not use standard layout");
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// TODO: MSVC does not support using offsetof() on non-static data members even though this
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// is technically allowed since C++11. This macro should be enabled once MSVC adds
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// support for that.
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#ifndef _MSC_VER
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Regs, field_name) == position * 4, \
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"Field "#field_name" has invalid position")
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ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
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ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
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ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
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ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
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ASSERT_REG_POSITION(display_transfer_config, 0x00300);
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ASSERT_REG_POSITION(command_processor_config, 0x00638);
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#undef ASSERT_REG_POSITION
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#endif // !defined(_MSC_VER)
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// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value anyway.
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static_assert(sizeof(Regs) == 0x1000 * sizeof(u32), "Invalid total size of register set");
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extern Regs g_regs;
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extern bool g_skip_frame;
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template <typename T>
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void Read(T &var, const u32 addr);
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template <typename T>
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void Write(u32 addr, const T data);
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/// Initialize hardware
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void Init();
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/// Shutdown hardware
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void Shutdown();
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} // namespace
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