99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
87 lines
3.2 KiB
C++
87 lines
3.2 KiB
C++
// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/surface.h"
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using VideoCore::Surface::BytesPerBlock;
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using VideoCore::Surface::PixelFormatFromRenderTargetFormat;
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namespace Tegra::Engines {
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Fermi2D::Fermi2D() {
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// Nvidia's OpenGL driver seems to assume these values
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regs.src.depth = 1;
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regs.dst.depth = 1;
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}
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Fermi2D::~Fermi2D() = default;
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void Fermi2D::BindRasterizer(VideoCore::RasterizerInterface* rasterizer_) {
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rasterizer = rasterizer_;
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}
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void Fermi2D::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Fermi2D register, increase the size of the Regs structure");
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regs.reg_array[method] = method_argument;
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if (method == FERMI2D_REG_INDEX(pixels_from_memory.src_y0) + 1) {
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Blit();
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}
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}
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void Fermi2D::CallMultiMethod(u32 method, const u32* base_start, u32 amount, u32 methods_pending) {
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for (u32 i = 0; i < amount; ++i) {
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CallMethod(method, base_start[i], methods_pending - i <= 1);
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}
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}
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void Fermi2D::Blit() {
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LOG_DEBUG(HW_GPU, "called. source address=0x{:x}, destination address=0x{:x}",
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regs.src.Address(), regs.dst.Address());
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UNIMPLEMENTED_IF_MSG(regs.operation != Operation::SrcCopy, "Operation is not copy");
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UNIMPLEMENTED_IF_MSG(regs.src.layer != 0, "Source layer is not zero");
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UNIMPLEMENTED_IF_MSG(regs.dst.layer != 0, "Destination layer is not zero");
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UNIMPLEMENTED_IF_MSG(regs.src.depth != 1, "Source depth is not one");
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UNIMPLEMENTED_IF_MSG(regs.clip_enable != 0, "Clipped blit enabled");
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const auto& args = regs.pixels_from_memory;
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Config config{
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.operation = regs.operation,
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.filter = args.sample_mode.filter,
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.dst_x0 = args.dst_x0,
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.dst_y0 = args.dst_y0,
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.dst_x1 = args.dst_x0 + args.dst_width,
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.dst_y1 = args.dst_y0 + args.dst_height,
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.src_x0 = static_cast<s32>(args.src_x0 >> 32),
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.src_y0 = static_cast<s32>(args.src_y0 >> 32),
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.src_x1 = static_cast<s32>((args.du_dx * args.dst_width + args.src_x0) >> 32),
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.src_y1 = static_cast<s32>((args.dv_dy * args.dst_height + args.src_y0) >> 32),
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};
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Surface src = regs.src;
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const auto bytes_per_pixel = BytesPerBlock(PixelFormatFromRenderTargetFormat(src.format));
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const auto need_align_to_pitch =
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src.linear == Tegra::Engines::Fermi2D::MemoryLayout::Pitch &&
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static_cast<s32>(src.width) == config.src_x1 &&
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config.src_x1 > static_cast<s32>(src.pitch / bytes_per_pixel) && config.src_x0 > 0;
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if (need_align_to_pitch) {
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auto address = src.Address() + config.src_x0 * bytes_per_pixel;
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src.addr_upper = static_cast<u32>(address >> 32);
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src.addr_lower = static_cast<u32>(address);
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src.width -= config.src_x0;
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config.src_x1 -= config.src_x0;
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config.src_x0 = 0;
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}
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if (!rasterizer->AccelerateSurfaceCopy(src, regs.dst, config)) {
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UNIMPLEMENTED();
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}
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}
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} // namespace Tegra::Engines
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